Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Optimised HEVC encoder intra-only configuration

  • Author(s): Nejmeddine Bahri 1  and  Randa Khemiri 2
    • View affiliations
  • Source: Volume 14, Issue 6, November 2020, p. 256 – 262
    DOI:  10.1049/iet-cdt.2019.0197 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Received 19/10/2019, Accepted 17/07/2020, Revised 07/06/2020, Published 12/08/2020

High-efficiency video coding (HEVC) is the latest video coding standard aimed to reduce the bitrate by half for the same video quality compared to H.264/AVC. This encoding performance makes HEVC more suitable for high-definition video applications. However, this performance is coupled with a high-computational complexity, which makes it hard to achieve real-time video encoding with a classic embedded processor. Multicore technology of programmable processors could be a very promising solution to overcome this computational complexity. Moreover, software optimisations by proposing fast algorithms for the most complex functions could also be an efficient solution to speed up the encoding process. In this context, this study presents a fast mode decision algorithm for the intra prediction module. This algorithm aims to reduce the number of intra prediction modes to be tested instead of performing a full intra mode search. Experimental results for all-Intra configuration show that the proposed fast intra mode decision allows saving up to 46.79% of the intra prediction time in average. Encoding performance in terms of video quality and bitrate is not significantly affected.

Inspec keywords: video coding; high definition video; data compression; optimisation; computational complexity

Other keywords: high-efficiency video coding; video quality; multicore technology; high-computational complexity; real-time video encoding; high-definition video applications; intra prediction modes; HEVC encoder intra-only configuration optimization; software optimisations; video coding standard; embedded processor

Subjects: Video signal processing; Computational complexity; Optimisation techniques; High definition television and video; Optimisation techniques; Image and video coding

References

    1. 1)
      • 5. Kim, H., Park, R.: ‘Fast CU partitioning algorithm for HEVC using an online learning-based Bayesian decision rule’, IEEE Trans. Circuits Syst. Video Technol., 2016, 26, (1), pp. 130–138.
    2. 2)
      • 4. Kibeya, H., Belghith, F., Ben Ayed, M. A., et al: ‘Fast intra-prediction algorithms for high efficiency video coding standard’, J. Electron. Imag., 2016, 25, (1), pp. 01–12.
    3. 3)
      • 23. Bjontegaard metric. Available at https://www.mathworks.com/matlabcentral/fileexchange/27798-bjontegaard-metric, accessed 11 March 2020.
    4. 4)
      • 19. Zhang, M., Qu, J., Bai, H.: ‘Fast intra prediction mode decision algorithm for hevc’, Indonesian J. Electr. Eng. Comput. Sci., 2013, 11, (10), pp. 5703–5710.
    5. 5)
      • 9. Azgin, H., Mert, A.C., Kalali, E., et al: ‘An efficient FPGA implementation of HEVC intra prediction’. IEEE Int. Conf. on Consumer Electronics (ICCE), Las Vegas, 2018, pp. 1–5.
    6. 6)
      • 20. Wei, L., Rangding, W., Jiaji, W., et al: ‘A fast mode decision algorithm for intra prediction in HEVC’. 3rd Int. Conf. on Computer Science and Service System (CSSS), Bangkok, Thailand, 2014, pp. 587–590.
    7. 7)
      • 6. Lim, K., Lee, J., Kim, S., et al: ‘Fast PU skip and split termination algorithm for HEVC intra prediction’, IEEE Trans. Circuits Syst. Video Technol., 2015, 25, (8), pp. 1335–1346.
    8. 8)
      • 22. ʻHEVC Elecard Analyzer’. Available at https://www.elecard.com/products/video-analysis/streameye-studio, accessed 11 March 2020.
    9. 9)
      • 13. Da Silva, T., Agostini, L., Da Silva Cruz, L.: ‘HEVC intra prediction acceleration based on texture direction and prediction unit modes reuse’, APSIPA Trans. Signal Inf. Process., 2014, 3, (13), pp. 01–13.
    10. 10)
      • 25. Chen, J., Chien, W.J., Karczewicz, M., et al: ‘Further improvements to HMKTA-1.0’. ITU-T SG16/Q6, Doc. VCEG-AZ07, 52nd Meeting, Geneva, Switzerland, 2015.
    11. 11)
      • 3. Yi, H., Qin, H.: ‘The optimization of HEVC intra prediction mode selection’. 4th Int. Conf. on Information Science and Control Engineering (ICISCE), Changsha, 2017, pp. 1743–1748.
    12. 12)
      • 7. Khemiri, R., Kibeya, H., Sayadi, F.E., et al: ‘Optimization of HEVC motion estimation exploiting SAD and SSD GPU-based implementation’, IET Image Process., 2018, 12, (2), pp. 243–253.
    13. 13)
      • 18. Gao, Y., Wu, X., Li, Y., et al: ‘A fast depth determination algorithm for high efficiency video coding’. 2nd Int. Conf. On Electrical, Computer Engineering And Electronics (ICECEE), Jinan, China, 2015, pp. 1175–1180.
    14. 14)
      • 21. Luo, F., Wang, S., Ma, S., et al: ‘Fast intra coding unit size decision for HEVC with GPU based keypoint detection’. IEEE Int. Symp. on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1–4.
    15. 15)
      • 17. Lin, Y., Lai, J.: ‘Fast depth-correlation algorithm for intra coding in HEV’, Int. J. Sci. Eng., 2014, 4, (2), pp. 269–272.
    16. 16)
      • 14. Bai, C., Yuan, C.: ‘Fast coding tree unit decision for HEVC intra coding’. IEEE Int. Conf. on Consumer Electronics, China, Shenzhen, 2013, pp. 28–31.
    17. 17)
      • 10. Maazouz, M., Bahri, N., Batel, N., et al: ‘Parallel implementation of Kvazaar HEVC on multicore ARM processor’. 8th Int. Conf. on Modelling, Identification and Control (ICMIC), Algiers, 2016, pp. 1086–1091.
    18. 18)
      • 15. Shi, W., Jiang, X., Song, T., et al: ‘Edge information based fast selection algorithm for intra prediction of HEVC’. IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), Ishigaki, 2014, pp. 17–20.
    19. 19)
      • 24. Lin, T., Jiang, H., Huang, J., et al: ‘Fast intra coding unit partition decision in H.266/FVC based on spatial features’, J. Real-Time Image Process., 2018, 17, (3), pp. 493–510.
    20. 20)
      • 16. Silva, T.L., Agostini, L.V., Cruz, L.A.: ‘Fast HEVC intra prediction mode decision based on EDGE direction information’. Proc. 20th European Signal Processing Conf. (EUSIPCO), Bucharest, Romania, 2012, pp. 1214–1218.
    21. 21)
      • 1. Bahri, N., Belhadj, N., Grandpierre, T., et al: ‘Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera’, J. Real-Time Image Process., 2016, 12, (4), pp. 791–812.
    22. 22)
      • 2. ‘High Efficiency Video Coding (HEVC) Test Model 16 (HM 16) Improved Encoder description’. Available at http://mpeg.chiariglione.org/sites/default/files/files/standards/parts/docs/w14970-v2-w14970.zip, accessed 19 october 2019.
    23. 23)
      • 8. Ahn, Y., Hwang, T., Sim, D., et al: ‘Implementation of fast HEVC encoder based on SIMD and data-level parallelism’, Eurasip J. Image Video Process., 2014, 1, (16), pp. 1–19.
    24. 24)
      • 12. Cebrián-Márquez, G., Galiano, V., Migallón, H., et al: ‘Heterogeneous CPU plus GPU approaches for HEV’, J. Supercomput., 2018, 75, (3), pp. 1215–1226.
    25. 25)
      • 11. Cebrián-Márquez, G., Hernández-Losada, J.L., Martínez, J.L., et al: ‘Accelerating HEVC using heterogeneous platforms’, J. Supercomput., 2015, 71, (2), pp. 613–628.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2019.0197
Loading

Related content

content/journals/10.1049/iet-cdt.2019.0197
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address