Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

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In this study, high-throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ( and ). The S-box is implemented based on area-optimised combinational logic circuits. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S-box consists of three steps: a field inversion over and two affine transformations over . The inversion operation is implemented over the composite field instead of inversion over which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.


    1. 1)
      • 1. Hatzivasilis, G., Fysarakis, K., Papaefstathiou, I., et al: ‘A review of lightweight block ciphers’, J. Cryptogr. Eng., 2018, 8, (2), pp. 141184.
    2. 2)
      • 2. Mohd, B.J., Hayajneh, T., Vasilakos, A.V.: ‘A survey on lightweight block ciphers for low-resource devices: comparative study and open issues’, J. Cryptogr. Eng., 2015, 58, pp. 7393.
    3. 3)
      • 3. Kitsos, P., Sklavos, N., Parousi, M., et al: ‘A comparative study of hardware architectures for lightweight block ciphers’, J. Cryptogr. Eng., 2012, 38, pp. 148160.
    4. 4)
      • 4. Rezaeian Farashahi, R., Rashidi, B., Sayedi, S.M.: ‘FPGA based fast and high-throughput 2-slow retiming 128 14;bit AES encryption algorithm’, Microelectron. J., 2014, 45, pp. 10141025.
    5. 5)
      • 5. The 128 bit block cipher CLEFIA: algorithm specification, Sony Corporation, Version 1, 2010.
    6. 6)
      • 6. Shirai, T., Shibutani, K., Akishita, T., et al: ‘The 128 14;bit block cipher CLEFIA (extended abstract)’. Proc. Int. Workshop on Fast Software Encryption, Luxembourg, 2007 (LNCS, 4593), pp. 181195.
    7. 7)
      • 7. CLEFIA standardization in ISO/IEC 29192-2. Available at, accessed in November 2012.
    8. 8)
      • 8. Akishita, T., Hiwatari, H.: ‘Very compact hardware implementations of the block cipher CLEFIA’. Proc. Int. Workshop on Selected Areas in Cryptography, Toronto, Canada, 2012 (LNCS, 7118), pp. 278292.
    9. 9)
      • 9. Sugawara, T., Homma, N., Aoki, T., et al: ‘High-performance ASIC implementations of the 128 14;bit block cipher CLEFIA’. Proc. Int. Workshop on Selected Areas in Cryptography, Seattle, WA, USA, 2008 (LNCS, 7118), pp. 29252928.
    10. 10)
      • 10. Mozaffari-Kermani, M., Azarderakhsh, R.: ‘Efficient fault diagnosis schemes for reliable lightweight cryptographic ISO/IEC standard CLEFIA benchmarked on ASIC and FPGA’, IEEE Trans. Ind. Electron., 2013, 60, (12), pp. 59255932.
    11. 11)
      • 11. Chaves, R.: ‘Embedded systems design with FPGA: compact CLEFIA implementation on FPGAs’ (Springer, New York, 2013, 1st edn.), pp. 225243.
    12. 12)
      • 12. Resende, J.C., Chaves, R.: ‘Dual CLEFIA/AES cipher core on FPGA’. Proc. Int. Symp. Applied Reconfigurable Computing, Bochum, Germany, 2015 (LNCS, 9040), pp. 229240.
    13. 13)
      • 13. Kryjak, T., Gorgon, M.: ‘Pipeline implementation of the 128 14;bit block cipher CLEFIA in FPGA’. Proc. Int. Conf. Field Programmable Logic and Applications, Prague, Czech Republic, 2009, pp. 373378.
    14. 14)
      • 14. Suryawanshi, V.A., Manna, G.C., Dorale, S.S.: ‘Compact and high-speed hardware implementation of the block – cipher clefia’, Int. J. Comput. Appl., 2016, 133, (8), pp. 1720.
    15. 15)
      • 15. Proenca, T., Chaves, R.: ‘Compact CLEFIA implementation on FPGAS’. Proc. 21st Int. Conf. Field Programmable Logic and Applications, Chania, Greece, 2012, pp. 512517.
    16. 16)
      • 16. Bittencourt, J.C., Resende, J.C., Oliveira, W.L., et al: ‘CLEFIA implementation with full key expansion’. Proc. Euromicro Conf. Digital System Design, Funchal, Portugal, 2015, pp. 555558.
    17. 17)
      • 17. Hanley, N., Neill, M.: ‘Hardware comparison of the ISO/IEC 29192-2 block ciphers’. Proc. Computer Society Annual Symp. VLSI, Amherst, MA, USA, 2012, pp. 5762.
    18. 18)
      • 18. Rudra, A., Dubey, P.K., Jutla, C.S., et al: ‘Efficient Rijndael encryption implementation with composite field arithmetic’. Proc. Cryptographic Hardware and Embedded Systems (CHES), Paris, France, 2001 (LNCS, 2162), pp. 171184.
    19. 19)
      • 19. Paar, C.: ‘Efficient VLSI architectures for bit-parallel computation in Galois fields’. PhD thesis, Institute for Experimental Mathematics, University of Essen, Essen, Germany, June 1994.
    20. 20)
      • 20. Rashidi, B., Sayedi, S.M., Rezaeian Farashahi, R.: ‘Efficient implementation of bit-parallel fault-tolerant polynomial basis multiplication and squaring over GF(2m)’, IET Comput. Digit. Tech., 2016, 10, (1), pp. 1829.
    21. 21)
      • 21. Rashidi, B., Rezaeian Farashahi, R., Sayedi, S.M.: ‘Fast and pipelined bit-parallel Montgomery multiplication and squaring over GF(2m)’. Proc. 12th Int. Iranian Society of Cryptology Information Security and Cryptology (ISCISC), Gillan, Iran, 2015, pp. 1722.
    22. 22)
      • 22. Stillmaker, A., Baas, B.: ‘Scaling equations for the accurate prediction of CMOS device performance from 180 to 7 nm’, Integr. VLSI J., 2017, 58, pp. 7481.
    23. 23)
      • 23. Wong, H.-S., Frank, D.J., Solomon, P., et al: ‘Nanoscale CMOS’, Proc. IEEE, 1999, 87, (4), pp. 537570.

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