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Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors

Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors

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In dynamic power dominated FinFET-based microprocessors, there is significant heterogeneity in the chip power profile induced due to various factors. The workloads the microprocessors operate on are inherently heterogeneous in their switching characteristics. There is also variation in power across the chip, even within the IP block for a given workload. The aim is to provide a comprehensive industry perspective on analysing and mitigating the problems and challenges posed by this heterogeneity in dynamic power signatures in the design of next generation 14 nm FinFET-based microprocessors like IBM POWER9. This broader view of design principles from a modern-day microprocessor like POWER9 is useful for the adoption of the techniques presented and further fuel-related research in the area of dynamic power management of FinFET-based microprocessor designs. Additional focus in the context of clock-gating techniques and other use cases is also placed. New approaches for heterogeneity-aware per clock-gating domain parameterised power abstractions for enabling rapid hierarchical chip power analysis are presented.


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