Scheduling of dual supercapacitor for longer battery lifetime in safety-critical embedded systems with power gating

Scheduling of dual supercapacitor for longer battery lifetime in safety-critical embedded systems with power gating

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The wake up of power gating (PG) components leads to flow of inrush current which quickly discharges the battery. An arrangement of instruction controlled hybrid battery supercapacitor (SC) elongates battery life in systems with PG. The present work improves a batterysingle SC system (BSC) model to its equivalent batterydual SC system (B2SC). Instructions: disconnect battery (db) and connect battery (cb) have been introduced along with architectural support for B2SC. During wakeup db disconnects (i) battery from the PG components, and (ii) either one or both of the SCs from the battery. Hence, simultaneously either both SCs can discharge or one can discharge while the other's charging. While cb connects the battery to the PG components and SCs. A suboptimal version of B2SC (B2SCsopt) is introduced, where the SCs are connected to the PG components requiring higher inrush current while rest remains connected to the battery. The efficacy of the proposed methods are evaluated on cardiac pacemaker, unmanned aerial vehicle and benchmark programmes. B2SC reduces battery ratecapacityeffect (Crate) by an average of 21.87% at the cost of average performance loss of 9.25%. (B2SCsopt) reduces Crate by an average of 29.37% at the cost of average performance loss of 16.87%.


    1. 1)
      • 1. Dougal, R.A., Liu, S., White, E.R.: ‘Power and life extension of battery-ultracapacitor hybrids’, IEEE Trans. Compon. Packag. Technol., 2002, 25, (1), pp. 120131.
    2. 2)
      • 2. Pyne, S.: ‘Scheduling of hybrid battery-supercapacitor control instructions for longevity in systems with power gating’. Proc. ACM/IEEE Int. Symp. Low Power Electronics and Design, Seattle, WA, USA, July 2018, pp. 45:145:6.
    3. 3)
      • 3. Wu, Q., Qiu, Q., Pedram, M.: ‘An interleaved dual-battery power supply for battery operated electronics’. Proc. Asia and South Pacific Design Automation Conf., Yokohama, Japan, January 2000, pp. 387390.
    4. 4)
      • 4. Benini, L., Castelli, G., Macii, A., et al: ‘Battery-driven dynamic power management of portable systems’. Proc. ACM/IEEE Int. Symp. System Synthesis, Madrid, Spain, September 2000, pp. 2533.
    5. 5)
      • 5. Benini, L., Castelli, G., Macii, A., et al: ‘Extending lifetime of portable systems by battery scheduling’. Proc. Conf. Design Automation and Test in Europe, Munich, Germany, March 2001, pp. 197201.
    6. 6)
      • 6. Chiasserini, C., Rao, R.: ‘Energy efficient battery management’, IEEE J. Sel. Areas Commun., 2001, 19, (7), pp. 12351245.
    7. 7)
      • 7. Rao, V., Singhal, G., Kumar, A., et al: ‘Battery model for embedded systems’. Proc. Int. Conf. VLSI Design and Int. Conf. Embedded Systems, Kolkata, India, January 2005, pp. 105110.
    8. 8)
      • 8. Rong, P., Pedram, M.: ‘Battery-aware power management based on Markovian decision processes’. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2006, 25, (7), pp. 13371349.
    9. 9)
      • 9. Shin, D., Kim, Y., Seo, J., et al: ‘Battery-supercapacitor hybrid system for high-rate pulsed load applications’. Proc. Conf. Design Automation and Test in Europe, Grenoble, France, March 2011, pp. 14.
    10. 10)
      • 10. Narayanaswamy, S., Schlueter, S., Steinhorst, S., et al: ‘On battery recovery effect in wireless sensor nodes’, ACM Trans. Des. Autom. Electron. Syst., 2016, 21, (4), pp. 60:160:28.
    11. 11)
      • 11. Available at Support/TechnicalDocument/AN024 Accessed: August: 2017.
    12. 12)
      • 12. Barold, S.S., Stroobandt, R.X., Sinnaeve, A.F.: ‘Cardiac pacemakers step by step’ (Futura Publishing, New York, NY, USA, 2004).
    13. 13)
      • 13. Hesselon, A.: ‘Simplified interpretations of pacemaker ECGs’ (Blackwell Publishers, New York, NY, USA, 2003).
    14. 14)
      • 14. Wong, L.S.Y., Hossain, S., Ta, A., et al: ‘A very low-power CMOS mixed-signal IC for implantable pacemaker applications’, IEEE J. Solid-State Circuits, 2004, 39, (12), pp. 24462456.
    15. 15)
      • 15. Available at, Accessed: January 2014.
    16. 16)
      • 16. Technical Report, ‘Pacemaker system specification’ (Boston Scientific, Boston, MA, USA2007). Available at, Accessed: October 2018.
    17. 17)
      • 17. Singh, N.K., Wellings, A., Cavalcanti, A.: ‘The cardiac pacemaker case study and its implementation in safety-critical Java and Ravenscar Ada’. Proc. Int. Workshop on Java Technologies for Real-time and Embedded Systems, Copenhagen, Denmark, October 2012, pp. 6271.
    18. 18)
      • 18. ArduPilot Mega, the Open Source Autopilot. Available at, Accessed: November 2018.
    19. 19)
      • 19. Arduino Mega 2560. Available at, Accessed: November 2018.
    20. 20)
      • 20. ATmega2560 – 8-bit AVR Microcontrollers, Microchip Technology. Available at, Accessed: November 2018.
    21. 21)
      • 21. Stevens ME 491 UAV Project 2012–13. Available at, Accessed: November 2018.
    22. 22)
      • 22. Guthaus, M.R., Ringenberg Jeffrey, S., Ernst, D., et al: ‘MiBench: a free, commercially representative embedded benchmark suite’. IEEE Fourth Annual Workshop on Workload Characterization, Austin, TX, USA, December 2001. Available at, Accessed: April 2017.
    23. 23)
      • 23. Lee, C., Potkonjak, M., Mangione-Smith, W.: ‘MediaBench: a tool for evaluating and synthesizing multimedia and communications systems’. Int. Symp. Microarchitecture,, Research Triangle Park, NC, USA, 1997. Available at, Accessed: April 2017.
    24. 24)
      • 24. The gem5 simulator: a modular platform for computer-system architecture research. Available at, Accessed: August 2016.
    25. 25)
      • 25. Li, S., Ahn, J.H., Strong, R.D., et al: ‘The McPAT framework for multicore and manycore architectures: simultaneously modeling power, area, and timing’, ACM Trans. Archit. Code Opt., 2013, 10, (1), pp. 5:15:29. Available at, DOI: 10.1145/2445572.2445577, Accessed: October 2012.
    26. 26)
      • 26. GNU ARM embedded toolchain. Available at, Accessed: December 2016.
    27. 27)
      • 27. You, Y.P., Lee, C., Lee, J.K.: ‘Compilers for leakage power reduction’, ACM Trans. Des. Autom. Electron. Syst., 2006, 11, (1), pp. 147164.
    28. 28)
      • 28. Roy, S., Katkoori, S., Ranganathan, N.: ‘A framework for power-gating functional units in embedded microprocessors’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2009, 17, (11), pp. 16401649.

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