Ultra-low power digital front-end for single lead ECG acquisition integrated with a time-to-digital converter

Ultra-low power digital front-end for single lead ECG acquisition integrated with a time-to-digital converter

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A low power single lead electrocardiogram front-end acquisition system in 0.18 μm CMOS operating at 0.5 V is presented here. The analogue blocks in low noise amplifier (LNA), filters and passive elements that perform amplification and DC offset cancellation are replaced by a moving average voltage to time converter (MA-VTC) to get amplification and anti-aliasing in the time domain. A digital feedback algorithm is used to cancel out the DC offset. The front-end structure is designed in the sub-threshold region of MOS to reduce the power consumption in the circuit. The proposed architecture consumes 50 nW of power with a gain of 670 μs/V. The output of the front-end is fed to an all digital time-to-digital converter (TDC) that operates in the near threshold region with a resolution of 586.4 ps and 32.5 μW power consumption.


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