access icon free Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Wide-spread availability of high-speed INTERNET and rapid increase of smart-phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1 kb (32 × 32) heterogeneous 8T SRAM architectures with (2-lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit-truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3 µW/pixel and 5.2 µm2/pixel, respectively, at 0.5 V and 20 MHz in UMC 28 nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.

Inspec keywords: SRAM chips; CMOS integrated circuits; low-power electronics; memory architecture; decoding; integrated circuit design; video coding

Other keywords: size 28.0 nm; bit-truncation techniques; low power memory design; heterogeneous 8T SRAM architectures; Hetro8T; voltage 0.5 V; frequency 20.0 MHz; UMC 28 nm CMOS technology; online video surfing; H.265 video decoder; approximate memory; heterogeneous sized SRAM design; MPEG video decoder; high-speed Internet; high video quality; H.264 video decoder; static random access memory buffers; low area budget; memory architecture

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Storage system design; CMOS integrated circuits; Image and video coding; Semiconductor storage; Memory circuits; Video signal processing

References

    1. 1)
      • 19. Giterman, R., Fish, A., Geuli, N., et al: ‘An 800-mhz mixed-VT 4t IFGC embedded dram in 28-nm cmos bulk process for approximate storage applications’, IEEE J. Solid-State Circuits, 2018, 53, (7), pp. 113.
    2. 2)
      • 3. Kim, H., Chang, I.J., Lee, H.J.: ‘Optimal selection of SRAM bit-cell size for power reduction in video compression’, IEEE J. Emerg. Sel. Top. Circuits Syst., 2018, 8, pp. 431443.
    3. 3)
      • 29. Sampson, A., Nelson, J., Strauss, K., et al: ‘Approximate storage in solid-state memories’, ACM Trans. Comput. Syst., 2014, 32, (3), p. 9.
    4. 4)
      • 17. Meinerzhagen, P., Teman, A., Giterman, R., et al: ‘Exploration of sub-VT and near-VT 2t gain-cell memories for ultra-low power applications under technology scaling’, J. Low Power Electron. Appl., 2013, 3, (2), pp. 5472.
    5. 5)
      • 7. Kwon, J., Chang, I.J., Lee, I., et al: ‘Heterogeneous SRAM cell sizing for low-power H.264 applications’, IEEE Trans. Circuits Syst. I, Regul.Pap., 2012, 59, (10), pp. 22752284.
    6. 6)
      • 30. Chang, M.T., Rosenfeld, P., Lu, S.L., et al: ‘Technology comparison for large last-level caches (l 3 cs): low-leakage SRAM, low write-energy STT-ram, and refresh-optimized EDRAM’. 2013 IEEE 19th Int. Symp. on High Performance Computer Architecture (HPCA2013), Shenzhen, China, 2013, pp. 143154.
    7. 7)
      • 4. Gong, N., Pourbakhsh, S.A., Chen, X., et al: ‘Spider: sizing-priority-based application-driven memory for mobile video applications’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (9), pp. 26252634.
    8. 8)
      • 12. Kazimirsky, A., Teman, A., Edri, N., et al: ‘A 0.65-v, 500-mhz integrated dynamic and static ram for error tolerant applications’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (9), pp. 24112418.
    9. 9)
      • 26. Zeinali, B., Karsinos, D., Moradi, F.: ‘Progressive scaled STT-ram for approximate computing in multimedia applications’, IEEE Trans. Circuits Syst. II, Express Briefs, 2018, 65, (7), pp. 938942.
    10. 10)
      • 20. Lin, C.C., Chen, J.W., Chang, H.C., et al: ‘A 160 k gates/4.5 KB SRAM H. 264 video decoder for HDTV applications’, IEEE J. Solid-State Circuits, 2007, 42, (1), pp. 170182.
    11. 11)
      • 5. Chang, I.J., Mohapatra, D., Roy, K.: ‘A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications’, IEEE Trans. Circuits Syst. Video Technol., 2011, 21, (2), pp. 101112.
    12. 12)
      • 23. Available http://trace.eas.asu.edu/yuv.
    13. 13)
      • 9. Gong, N., Jiang, S., Challapalli, A., et al: ‘Ultra-low voltage split-data-aware embedded SRAM for mobile video applications’, IEEE Trans. Circuits Syst. II, Express Briefs, 2012, 59, (12), pp. 883887.
    14. 14)
      • 22. Bharti, P.K., Surana, N., Mekie, J.: ‘Power and area efficient approximate heterogeneous 8T SRAM for multimedia applications’. 2019 32nd Int. Conf. on VLSI Design and 2019 18th Int. Conf. on Embedded Systems (VLSID), New Delhi, India, 2019, pp. 139144.
    15. 15)
      • 1. Cisco systems, Inc: Available at https://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/white-paper-c11-741490.html.
    16. 16)
      • 6. Weste, N.H., Harris, D.: ‘CMOS VLSI design: a circuits and systems perspective’ (Pearson Education India, London, UK, 2015).
    17. 17)
      • 11. Surana, N., Mekie, J.: ‘Energy efficient single-ended 6T SRAM for multimedia applications’, IEEE Trans. Circuits Syst. II, Express Briefs, 2018, 66, pp. 10231027.
    18. 18)
      • 13. Rabaey, J.M., Chandrakasan, A.P., Nikolic, B.: ‘Digital integrated circuits’, vol. 2 (Prentice hall, Englewood Cliffs, NJ, USA, 2002).
    19. 19)
      • 18. Giterman, R., Teman, A., Meinerzhagen, P., et al: ‘Single-supply 3T gain-cell for low-voltage low-power applications’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24, (1), pp. 358362.
    20. 20)
      • 21. Chien, S.Y., Huang, Y.W., Chen, C.Y., et al: ‘Hardware architecture design of video compression for multimedia communication systems’, IEEE Commun. Mag., 2005, 43, (8), pp. 123131.
    21. 21)
      • 16. Apalkov, D., Khvalkovskiy, A., Watts, S., et al: ‘Spin-transfer torque magnetic random access memory (STT-MRAM)’, ACM J. Emerg. Technol. Comput. Syst., 2013, 9, (2), p. 13.
    22. 22)
      • 14. Chang, L., Montoye, R.K., Nakamura, Y., et al: ‘An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 956963.
    23. 23)
      • 24. Mahdiani, H.R., Ahmadi, A., Fakhraie, S.M., et al: ‘Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications’, IEEE Trans. Circuits Syst. I, Regul.Pap., 2010, 57, (4), pp. 850862.
    24. 24)
      • 27. Rizk, R., Rizk, D., Kumar, A., et al: ‘Demystifying emerging nonvolatile memory technologies: understanding advantages, challenges, trends, and novel applications’, IEEE Int. Symp. on Circuits and Systems (ISCAS), Sapporo, Japan, 1 May 2019, pp. 15.
    25. 25)
      • 28. Lai, S.: ‘Current status of the phase change memory and its future’. IEEE Int. Electron Devices Meeting, 2003. IEDM'03 Technical Digest, Washington, DC, USA, 2003, pp. 1011.
    26. 26)
      • 2. (2012) the digital universe in 2020: Big data, bigger digital shadows, and biggest growth in the far east. December 2012’. Available at https://www.emc.com/collateral/analyst-reports/idc-digital-universe-united-states.pdf.
    27. 27)
      • 31. Tikekar, M., Huang, C.T., Juvekar, C., et al: ‘A 249-mpixel/s hevc video-decoder chip for 4k ultra-hd applications’, IEEE J. Solid-State Circuits, 2014, 49, (1), pp. 6172.
    28. 28)
      • 15. Xu, Y., Das, H., Gong, Y., et al: ‘On mathematical models of optimal video memory design’, IEEE Trans. Circuits Syst. Video Technol., 2019.
    29. 29)
      • 10. Chen, D., Edstrom, J., Gong, Y., et al: ‘Viewer-aware intelligent efficient mobile video embedded memory’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2018, 26, (4), pp. 684696.
    30. 30)
      • 25. Dalloo, A., Najafi, A., Garcia Ortiz, A.: ‘Systematic design of an approximate adder: the optimized lower part constant-or adder’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2018, 26, (8), pp. 15951599.
    31. 31)
      • 8. Ataei, S., Stine, J.E.: ‘A 64 KB approximate SRAM architecture for low-power video applications’, IEEE Embedded Sys. Lett., 2018, 10, (1), pp. 1013.
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