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access icon free Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct , , and twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.


    1. 1)
      • 19. Yu, C., Yen, M.-H., Hsiung, P.-A., et al: ‘A low-power 64-point pipeline FFT/IFFT processor for OFDM applications’, IEEE Trans. Consum. Electron., 2011, 57, (1), pp. 4040.
    2. 2)
      • 10. Lee, J., Lee, H., Cho, S.-I., et al: ‘A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems’. IEEE Int. Symp. on Circuits and Systems, Island of Kos, Greece, 2006.
    3. 3)
      • 7. Cortés, A., Vélez, I., Sevillano, J.F.: ‘Radix-rk FFTs: matricial representation and SDC/SDF pipeline implementation’, IEEE Trans. Signal Process., 2009, 57, (7), pp. 28242839.
    4. 4)
      • 13. He, S., Torkelson, M.: ‘A new approach to pipeline FFT processor’. Proc. Parallel Processing Symp., Honolulu, HI, USA, 1996, pp. 766770.
    5. 5)
      • 18. Ganjikunta, G.K., Sahoo, S.K.: ‘An area-efficient and low-power 64-point pipeline fast Fourier transform for OFDM applications’, Integr. VLSI J., 2017, 57, pp. 125131.
    6. 6)
      • 1. Sanduleac, M., Lipari, G., Monti, A., et al: ‘Next generation real-time smart meters for ICT based assessment of grid data inconsistencies’, Energies, 2017, 10, (7), p. 857.
    7. 7)
      • 4. Hossain, M.R., Oo, A.M.T., Ali, A.S.: ‘Evolution of smart grid and some pertinent issues’. Australasian Universities Power Engineering Conf., Christchurch, New Zealand, 2010, pp. 16.
    8. 8)
      • 6. Cooley, J.W., Tukey, J.W.: ‘An algorithm for the machine calculation of complex Fourier series’, Math. Comput., 1965, 19, (90), pp. 297301.
    9. 9)
      • 2. Viciana, E., Alcayde, A., Montoya, F.G., et al: ‘Openzmeter: an efficient low-cost energy smart meter and power quality analyzer’, Sustainability, 2018, 10, (11), p. 4038.
    10. 10)
      • 20. Lin, Y.-W., Liu, H.-Y., Lee, C.-Y.: ‘A 1-GS/s FFT/IFFT processor for UWB applications’, IEEE J. Solid-State Circuits, 2005, 40, (8), pp. 17261735.
    11. 11)
      • 12. Alves, D.C., da Silva, G.S., de Lima, E.R., et al: ‘Architecture design and implementation of key components of an OFDM transceiver for IEEE 802.15. 4g’. IEEE Int. Symp. on Circuits and Systems, Montreal, QC, Canada, 2016, pp. 550553.
    12. 12)
      • 14. Sansaloni, T., Perez-Pascual, A., Torres, V., et al: ‘Efficient pipeline FFT processors for WLAN MIMO-OFDM systems’, Electron. Lett., 2005, 41, (19), pp. 10431044.
    13. 13)
      • 11. Cho, T., Lee, H., Park, J., et al: ‘A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications’. IEEE Int. Symp. on Circuits and Systems, Rio de Janeiro, Brazil, Rio de Janeiro, Brazil, 2011, pp. 12591262.
    14. 14)
      • 21. Fu, B., Ampadu, P.: ‘An area efficient FFT/IFFT processor for MIMO-OFDM WLAN 802.11 n’, J. Signal. Process. Syst., 2009, 56, (1), pp. 5968.
    15. 15)
      • 16. Arunachalam, V., Raj, A.N.J.: ‘Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications’, IET Circuits Devices Syst., 2014, 8, (6), pp. 526531.
    16. 16)
      • 9. Adiono, T., Irsyadi, M.S., Hidayat, Y.S., et al: ‘64-point fast efficient FFT architecture using radix-23 single path delay feedback’. Int. Conf. on Electrical Engineering and Informatics, Selangor, Malaysia, 2009, vol. 2, pp. 654658.
    17. 17)
      • 5. IEEE std. 802.15.4g-2012: Part 15.4: ‘Wireless medium access control and physical layer specifications for low-rate wireless personal area networks amendment 4: physical layer specifications for low data rate wireless smart metering utility networks’, March 2012.
    18. 18)
      • 24. Li, N., Van Der Meijs, N.: ‘A radix-22 based parallel pipeline FFT processor for MB-OFDM UWB system’. IEEE Int. SOC Conf., Belfast, UK, 2009, pp. 383386.
    19. 19)
      • 3. Buzachis, A., Galletta, A., Celesti, A., et al: ‘Development of a smart metering microservice based on fast Fourier transform (FFT) for edge/internet of things environments’. 2019 IEEE 3rd Int. Conf. on Fog and Edge Computing (ICFEC), Larnaca, Cyprus, 2019, pp. 16.
    20. 20)
      • 22. Cho, S.-I., Kang, K.-M.: ‘A low-complexity 128-point mixed-radix FFT processor for MB-OFDM UWB systems’, ETRI J., 2010, 32, (1), pp. 110.
    21. 21)
      • 23. Sarada, V., Vigneswaran, T., Selvakumar, J.: ‘Low-power and high-throughput 128-point feedforward FFT processor’, Cluster Comput., 2019, 22, pp. 1339713404.
    22. 22)
      • 15. Kumar, G.G., Sahoo, S.K., Meher, P.K.: ‘50 years of FFT algorithms and applications’, Circuits Syst. Signal Process., 2019, 380, (12), pp. 56655698.
    23. 23)
      • 17. Maharatna, K., Grass, E., Jagdhold, U.: ‘A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM’, IEEE J. Solid-State Circuits, 2004, 39, (3), pp. 484493.
    24. 24)
      • 8. He, S., Torkelson, M.: ‘Design and implementation of a 1024-point pipeline FFT processor’. Proc. Custom Integrated Circuits Conf., Santa Clara, CA, USA, 1998, pp. 131134.

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