access icon free Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology

This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal-oxide-semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power-delay-product (pdp). Topologies namely direct, grouping, and divide-by-2 are simulated for and conventional 1-bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual-, dual- and supply switching with ground collapse (SSGC). 1-bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual-, dual-, and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high-performance applications with no area overhead.

Inspec keywords: circuit optimisation; leakage currents; integrated circuit design; CMOS logic circuits; adders; network topology; logic design; low-power electronics

Other keywords: size 16.0 nm; complementary metal-oxide-semiconductor technology; supply switching with ground collapse; static power dissipation; word length 1 bit; CMOS technology; dual gate oxide thickness; direct topology; design topologies; leakage reduction; SSGC techniques; dual-Vth assignment; adder circuit; dual-Tox assignment; dual threshold voltage; high-performance applications; circuit optimisation; power-delay-product; low power applications

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Digital circuit design, modelling and testing; Logic and switching circuits; Logic design methods; Logic circuits; CMOS integrated circuits

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