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access icon free Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology

This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal-oxide-semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power-delay-product (pdp). Topologies namely direct, grouping, and divide-by-2 are simulated for and conventional 1-bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual-, dual- and supply switching with ground collapse (SSGC). 1-bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual-, dual-, and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high-performance applications with no area overhead.

References

    1. 1)
      • 8. Lee, D., Blaauw, D.: ‘Static leakage reduction through simultaneous threshold voltage and state assignment’. Proc. 40th Annual Design Automation Conf., Anaheim, CA, USA, 2003, pp. 191194.
    2. 2)
      • 19. Krishnamurthy, R.K., Alvandpour, A., De, V., et al: ‘High-performance and low-power challenges for sub-70 nm microprocessor circuits’. Proc. CICC, Orlando, FL, USA, 2002, pp. 125128.
    3. 3)
      • 18. Singh, S., Kaushik, B.K., Dasgupta, S.: ‘A modified gate replacement algorithm for leakage reduction using dual-Tox in CMOS VLSI circuits’, in Gaur, M.S., Zwolinski, M., Laxmi, V. (Eds.): ‘VLSI design and test’ (Springer, India, 2013), pp. 146152.
    4. 4)
      • 5. Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: ‘Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits’, Proc. IEEE, 2003, 91, (2), pp. 305327.
    5. 5)
      • 6. Yeap, G.K.: ‘Practical low power digital VLSI design’ (Springer Science & Business Media, USA, 2012).
    6. 6)
      • 12. Singhal Smita, M.A., Nidhi, G.: ‘Sleep transistor sizing – impact on power and performance in deep-submicron technologies’, Int. J. Appl. Eng. Res., 2015, 10, (94), pp. 113117.
    7. 7)
      • 3. Rabaey, J.M., Pedram, M.: ‘Low power design methodologies’ vol. 336 (Springer Science & Business Media, USA, 2012).
    8. 8)
      • 25. Lee, D., Deogun, H., Blaauw, D., et al: ‘Simultaneous state, Vt and Tox assignment for total standby power minimization’. Proc. Conf. on Design, Automation and Test in Europe-Volume 1, Paris, France, 2004, p. 10494.
    9. 9)
      • 9. Piguet, C.: ‘Low-power electronics design’ (CRC Press, USA, 2004).
    10. 10)
      • 23. Singhal, S., Mehra, A.: ‘A novel technique for static leakage reduction in 16 nm CMOS design’, Int. J. Electron. Lett., 2018, 7, (4), pp. 434447.
    11. 11)
      • 15. Yu, B., Ju, D.-H., Lee, W.-C., et al: ‘Gate engineering for deep-submicron CMOS transistors’, IEEE Trans. Electron Devices, 1998, 45, (6), pp. 12531262.
    12. 12)
      • 2. Sharma, V.K., Pattanaik, M., Raj, B.: ‘INDEP approach for leakage reduction in nanoscale CMOS circuits’, Int. J. Electron., 2015, 102, (2), pp. 200215.
    13. 13)
      • 13. Mukhopadhyay, S., Neau, C., Cakici, R.T., et al: ‘Gate leakage reduction for scaled devices using transistor stacking’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2003, 11, (4), pp. 716730.
    14. 14)
      • 16. Amelifard, B., Fallah, F., Pedram, M.: ‘Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment’. Proc. IEEE Design, Automation and Test in Europe, 2006. DATE'06, Munich, Germany, 2006, vol. 1, pp. 16.
    15. 15)
      • 4. Butzen, P.F., Ribas, R.P.: ‘Leakage current in sub-micrometer CMOS gates’. Universidade Federal do Rio Grande do Sul, 2006, pp. 128.
    16. 16)
      • 22. Mukherjee, V., Mohanty, S.P., Kougianos, E.: ‘A dual dielectric approach for performance aware gate tunneling reduction in combinational circuits’. Proc. 2005 IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005, San Jose, CA, USA, 2005, pp. 431436.
    17. 17)
      • 1. Al-Hertani, H., Al-Khalili, D., Rozon, C.: ‘UDSM subthreshold leakage model for NMOS transistor stacks’, Microelectron. J., 2008, 39, (12), pp. 18091816.
    18. 18)
      • 11. Mutoh, S., Douseki, T., Matsuya, Y., et al: ‘1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS’, IEEE J. Solid-State Circuits, 1995, 30, (8), pp. 847854.
    19. 19)
      • 24. Naseri, H., Timarchi, S.: ‘Low-power and fast full adder by exploring new XOR and XNOR gates’, IEEE Trans. Very Large Scale Integr. (VLSI) Systems, 2018, 26, (8), pp. 14811493.
    20. 20)
      • 14. Singhal, S., Gaur, N., Mehra, A., et al: ‘Analysis and comparison of leakage power reduction techniques in CMOS circuits’. 2015 2nd Int. Conf. on Signal Processing and Integrated Networks (SPIN), Noida, India, 2015, pp. 936944.
    21. 21)
      • 10. Yeo, K.-S., Roy, K.: ‘Low voltage, low power VLSI subsystems’ (McGraw-Hill, Inc., USA, 2004).
    22. 22)
      • 7. Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: ‘Low-power CMOS digital design’, IEICE Trans. Electron., 1992, 75, (4), pp. 371382.
    23. 23)
      • 21. Sultania, A.K., Sylvester, D., Sapatnekar, S.S.: ‘Transistor and pin reordering for gate oxide leakage reduction in dual Tox circuits’. Proc. IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004, San Jose, CA, USA, 2004, pp. 228233.
    24. 24)
      • 17. Behnam, A., Farzan, F., Massoud, P.: ‘Leakage minimization of SRAM cells in a dual-Vt and dual-Tox technology’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2008, 16, (7), pp. 851860.
    25. 25)
      • 26. Ketkar, M., Sapatnekar, S.S.: ‘Standby power optimization via transistor sizing and dual threshold voltage assignment’. Proc. 2002 IEEE/ACM Int. Conf. on Computer-Aided Design, San Jose, CA, USA, 2002, pp. 375378.
    26. 26)
      • 20. Shin, Y., Heo, S., Kim, H.-O., et al: ‘Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2007, 15, (7), pp. 758766.
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