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access icon free Mapping application-specific topology to mesh topology with reconfigurable switches

© The Institution of Engineering and Technology
Received 25/10/2018, Accepted 30/07/2019, Revised 24/04/2019, Published 06/08/2019

When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors’ method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.

Inspec keywords: network-on-chip; network topology; network routing; energy consumption; low-power electronics; genetic algorithms; fault tolerance

Other keywords: network-on-chip architecture; regular NoC topologies; energy consumption; chip area; communicating nodes; reconfigurable switches; fault-tolerance capabilities; genetic algorithm; mesh topology; mapping application-specific topology; two-step method; irregular NoC topologies; routing path

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Electrical/electronic equipment (energy utilisation); Network topology; Network-on-chip; Digital circuit design, modelling and testing; Network-on-chip; Logic design methods; Optimisation techniques; Optimisation techniques

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