http://iet.metastore.ingenta.com
1887

Mitigating information leakage during critical communication using S*FSM

Mitigating information leakage during critical communication using S*FSM

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
You pay $16.00
(plus tax if applicable)
Buy Knowledge Pack
25 articles for $40.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Security-centric components and systems, such as System-on-Chip early-boot communication protocols and ultra-specific lightweight devices, require a departure from minimalist design constructs. The need for built-in protection mechanisms, at all levels of design, is paramount to providing cost-effective, efficient, secure systems. In this work, Securely derived Finite State Machines (S*FSM) and power-aware S*FSM are proposed and studied. Overall results show that to provide an S*FSM, the typical FSM requires a 50% increase in the number of states and a 57% increase in the number of product terms needed to define the state transitions. These increases translate to a minimum encoding space increase of 70%, raising the average encoding length from 4.8 bits to 7.9 bits. When factoring in relaxed structural constraints for power and space mitigation, the respective increases of 53 and 67% raise the average number of bits needed to 7.3 and 7.9. Regarding power savings, current minimisation is possible for both FSMs and S*FSMs through the addition of encoding constraints with average current reductions of 30 and 70%, respectively. Overall, a power-constrained S*FSM consumes about 5% more power than insecure FSMs with binary encodings, though with a penalty of a 95% increase in layout area.

References

    1. 1)
      • 1. Tiri, K., Akmal, M., Verbauwhede, I.: ‘A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards’. Proc. the 28th European Solid-State Circuits Conf. (ESSCIRC 2002), Florence, Italy, 2002, pp. 403406.
    2. 2)
      • 2. Tiri, K., Verbauwhede, I.: ‘A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation’. Proc. Design, Automation and Test in Europe Conference and Exhibition, Paris, France, 2004, pp. 246251.
    3. 3)
      • 3. Sundaresan, V., Rammohan, S., Vemuri, R.: ‘Power invariant secure IC design methodology using reduced complementary dynamic and differential logic’. IFIP Int. Conf. Very Large Scale Integration (VLSI – SoC 2007), Atlanta, GA, USA, 2007, pp. 16.
    4. 4)
      • 4. Ramakrishnan, L.N., Chakkaravarthy, M., Manchanda, A.S., et al: ‘SDMLp: on the use of complementary pass transistor logic for design of DPA resistant circuits’. 2012 IEEE Int. Symp. Hardware-Oriented Security and Trust (HOST), San Francisco, CA, USA, 2012.
    5. 5)
      • 5. Alagar, V., Periyasamy, K.: ‘Extended finite state machine’, in ‘Specification of software systems(Texts in Computer Science), (Springer, London, 2011), pp. 105128.
    6. 6)
      • 6. Jiang, Z., Pajic, M., Moarref, S., et al: ‘Modeling and verification of a dual chamber implantable pacemaker’, in ‘Tools and algorithms for the construction and analysis of systems’, (Springer, Berlin, Germany, 2012), pp. 188203.
    7. 7)
      • 7. Jiang, Z., Pajic, M., Mangharam, R.: ‘Cyber–physical modeling of implantable cardiac medical devices’, Proc. IEEE, 2012, 100, (1), pp. 122137.
    8. 8)
      • 8. Hwang, Y.-T., Lin, S.-C.: ‘Automatic protocol translation and template based interface synthesis for IP reuse in SoC’. Proc. the 2004 IEEE Asia-Pacific Conf. Circuits and Systems, Tainan, Taiwan, 2004, vol. 1, pp. 565568.
    9. 9)
      • 9. Zitouni, A., Badrouchi, S., Tourki, R.: ‘Communication architecture synthesis for multi-bus SoC’, J. Comput. Sci., 2006, 2, (1), pp. 6371.
    10. 10)
      • 10. Borowczak, M., Vemuri, R.: ‘S*FSM: an paradigm shift for attack resistant FSM designs and encodings’. Int. Conf. Cyber Security Redefining and Integrating Security Engineering (RISE 2012), Washington, DC, USA, 2012, pp. 651655.
    11. 11)
      • 11. Kocher, P., Jaffe, J., Jun, B.: ‘Differential power analysis’, in Wiener, M., (Ed.): ‘Advances in cryptology âĂŤ CRYPTOâĂŹ 99’, (LNCS, 1666), (Springer, Berlin/Heidelberg, 1999), pp. 789789.
    12. 12)
      • 12. Verbauwhede, I.: ‘Secure integrated circuits and systems, integrated circuits and systems’ (Springer London, Limited, 2010).
    13. 13)
      • 13. Mangard, S., Oswald, E., Popp, T.: ‘Power analysis attacks: revealing the secrets of smart cards’ (Advances in Information Security) (Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2007).
    14. 14)
      • 14. Schaumont, P., Tiri, K.: ‘Masking and dual-rail logic don't add up’, in Paillier, P., Verbauwhede, I., (Eds.): ‘Cryptographic hardware and embedded systems – CHES 2007’, (LNCS, 4727), (Springer, Berlin/Heidelberg, 2007), pp. 95106.
    15. 15)
      • 15. Macé, F., Standaert, F.-X., Quisquater, J.-J.: ‘Information theoretic evaluation of side-channel resistant logic styles’, in Paillier, P., Verbauwhede, I., (Eds.): ‘Cryptographic hardware and embedded systems - CHES’ 2007’, (LNCS, 4727), (Springer, Berlin/Heidelberg, 2007), pp. 427442.
    16. 16)
      • 16. Kulikowski, K., Smirnov, A., Taubin, A.: ‘Automated design of cryptographic devices resistant to multiple side-channel attacks’. Workshop on Cryptographic Hardware and Embedded Systems, Yokohama, Japan, 2006, pp. 339413.
    17. 17)
      • 17. Golić, J., Tymen, C.: ‘Multiplicative masking and power analysis of AES’, in Kaliski, B., Koetin, C.P., (Eds.): ‘Cryptographic hardware and embedded systems – CHES 2002’, (LNCS, 2523), (Springer, Berlin/Heidelberg, 2003), pp. 3147.
    18. 18)
      • 18. Oswald, E., Mangard, S., Pramstaller, N., et al: ‘A side-channel analysis resistant description of the AES S-Box’ (Fast Software Encryption, Springer, Berlin, Germany, 2005), pp. 413423.
    19. 19)
      • 19. Tiri, K., Hwang, D., Hodjat, A., et al: ‘Prototype IC with WDDL and differential routing – DPA resistance assessment’. In Cryptographic Hardware and Embedded Systems – CHES, Edinburgh, UK, 2005, pp. 354365.
    20. 20)
      • 20. Hennessy, J., Patterson, D., Arpaci-Dusseau, A.: ‘Computer architecture: a quantitative approach’, in ‘The Morgan Kaufmann series in computer architecture and design’, vol. 1 (Elsevier, New York, NY, USA, 2011), pp. C.27C.28.
    21. 21)
      • 21. Yeh, T.-Y., Patt, Y.N.: ‘Two-level adaptive training branch prediction’. Proc. the 24th Annual Int. Symp. Microarchitecture, MICRO 24, New York, NY, USA, 1991, pp. 5161.
    22. 22)
      • 22. Dietrich, M., Haase, J.: ‘Process variations and probabilistic integrated circuit design’ (Springer, New York, NY, USA, 2011).
    23. 23)
      • 23. Li, T., Zhang, W., Yu, Z.: ‘Full-chip leakage analysis in nanoscale technologies: mechanisms, variation sources, and verification’. 45th ACM/IEEE Design Automation Conf. (DAC 2008), Anaheim, CA, USA, 2008.
    24. 24)
      • 24. Shen, R., Tan, S.X. D., Yu, H.: ‘Statistical performance analysis and modeling techniques for nanometer VLSI designs’ (Springer, New York, NY, USA, 2012).
    25. 25)
      • 25. Johansson, J., Forskitt, J.: ‘System designs into silicon’ (Taylor & Francis, Abingdon, UK, 1993).
    26. 26)
      • 26. Cao, C., Oelmann, B.C.: ‘The analysis of power-related characteristics of FSM benchmarks’. 50th Midwest Symp. S.M. Circuits and Systems (MWSCAS 2007), Montreal, QC, Canada, 2007.
    27. 27)
      • 27. Koegst, M., Franke, G., Feske, K.D.A.C.W.E.-V., et al: ‘State assignment for FSM low power design’. Design Automation Conf., 1996, with EURO-VHDL ‘96 and Exhibition, Proc. EURO-DAC ‘96, European, Geneva, Switzerland, 1996.
    28. 28)
      • 28. Pasha, M.A., Derrien, S., Sentieys, O.C.: ‘Ultra low-power FSM for control oriented applications’. IEEE Int. Symp. Circuits and Systems (ISCAS), Taipei, Taiwan, 2009.
    29. 29)
      • 29. Akdemir, K.D., Sunar, B.C.D.T.I.: ‘Generic approach for hardening state machines against strong adversaries’, IET Comput. Digital Techn., 2010.
    30. 30)
      • 30. Moradmand, H., Payandeh, A.A.T.F.C.A.I.C.O.: ‘Secure finite state integer arithmetic codes’. 2011 Int. Conf. Advanced Technologies for Communications (ATC), Da Nang, Vietnam, 2011.
    31. 31)
      • 31. Wang, Z., Karpovsky, M.O.-L.T.S.I.I.T.I.: ‘Robust FSMs for cryptographic devices resilient to strong fault injection attacks’. 2010 IEEE 16th Int. Line Testing Symp. (IOLTS), Corfu, Greece, 2010.
    32. 32)
      • 32. Grune, D., Jacobs, C.: ‘Parsing techniques: a practical guideMonographs in computer science. (Springer, New York, NY, USA, 2008).
    33. 33)
      • 33. Cao, C., Oelmann, B.: ‘Mixed synchronous/asynchronous state memory for low power FSM design’. Euromicro Symp. Digital System Design (DSD 2004), Rennes, France, 2004, pp. 363370.
    34. 34)
      • 34. Gao, F., Hayes, J.: ‘ILP-based optimization of sequential circuits for low power’. Proc. of the 2003 Int. Symp. on Low Power Electronics and Design (ISLPED ‘03), Seoul, Republic of Korea, 2003, pp. 140145.
    35. 35)
      • 35. Huang, S.-H., Chang, C.-M., Nieh, Y.-T.: ‘State re-encoding for peak current minimization’. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD ‘06), San Jose, CA, USA, 2006, pp. 3338.
    36. 36)
      • 36. Lee, Y., Kim, T.: ‘State encoding algorithm for peak current minimisation’, IET Comput. Digital Techn., 2011, 5, (2), pp. 113122.
    37. 37)
      • 37. Olson, E., Kang, S.: ‘State assignment for low-power FSM synthesis using genetic local search’. Proc. the IEEE 1994 Custom Integrated Circuits Conf., San Diego, CA, USA, 1994, pp. 140143.
    38. 38)
      • 38. Yuan, L., Qu, G., Villa, T., et al: ‘FSM re-engineering and its application in low power state encoding’. Proc. the Asia and South Pacific Design Automation Conf. (ASP-DAC 2005), Shanghai, China, 2005, vol. 1, pp. 254259.
    39. 39)
      • 39. Jozwiak, L., Gawlowski, D., Slusarczyk, A.: ‘An effective solution of benchmarking problem: FSM benchmark generator and its application to analysis of state assignment methods’. Euromicro Symp. Digital System Design (DSD 2004), Rennes, France, 2004, pp. 160167.
    40. 40)
      • 40. Yang, S.: ‘Logic synthesis and optimization benchmarks user guide version 3.0’. 1991.
    41. 41)
      • 41. Popp, T., Mangard, S.: ‘Masked dual-rail pre-charge logic: DPA-resistance without routing constraints’. Proc. of the 7th Int. Conf. Cryptographic Hardware and Embedded Systems, CHES'05, Springer-Verlag, Berlin, Heidelberg, 2005, pp. 172186.
    42. 42)
      • 42. Bayrak, A.G., Velickovic, N., Regazzoni, F., et al: ‘An EDA-friendly protection scheme against side-channel attacks’. Proc. of the Conf. on Design, Automation and Test in Europe, San Jose, CA, USA, EDA Consortium, 2013, pp. 410415.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2018.5186
Loading

Related content

content/journals/10.1049/iet-cdt.2018.5186
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address