http://iet.metastore.ingenta.com
1887

Temperature-aware core management in MPSoCs: modelling and evaluation using MRMs

Temperature-aware core management in MPSoCs: modelling and evaluation using MRMs

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

With successive scaling of CMOS technology, power density and cooling costs significantly increase. Consequently, the cooling system of processors can no longer be designed for the worst-case situation in each generation of CMOS technology and there is an essential need for run-time techniques to control the operating temperature. Task scheduling and resource management with respect to thermal constraints are run-time methods used to control the thermal profile of a system. In this study, the authors use Markov Reward Models (MRMs) to model and evaluate a new core thermal management method, which can reduce hotspots and balance the thermal profile of a multi-core system. Although the proposed management method degrades the performance of the system, such as other previously presented methods, it controls the temperature of a die to decrease the temperature variation and hotspots. The proposed approach is assessed on a quad-core system and the experimental results are compared to the results obtained from the proposed MRM to demonstrate the accuracy of the proposed analytical model.

References

    1. 1)
      • 1. Zagan, I., Gheorghiţă, V.G.: ‘Implementation of nmpra cpu architecture based on preemptive hardware scheduler engine and different scheduling algorithms’, IET Comput. Digit. Tech., 2017, 6, (11), pp. 221230.
    2. 2)
      • 2. Wolf, W., Jerraya, A.A., Martin, G.: ‘Multiprocessor system-on-chip (MPSoC) technology’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2008, 27, (10), pp. 17011713.
    3. 3)
      • 3. Bhat, G., Gumussoy, S., Ogras, U.Y.: ‘Power-temperature stability and safety analysis for multiprocessor systems’, ACM Trans. Embedded Comput. Syst., 2017, 16, (5s), pp. 145:1145:19.
    4. 4)
      • 4. Taheri, G., Khonsari, A., Entezari-Maleki, R., et al: ‘Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using stochastic activity networks’, Microprocess. Microsyst., 2018, 60, (1), pp. 1523.
    5. 5)
      • 5. Lu, L., Chiou, L.: ‘Temperature gradient-aware thermal simulator for three-dimensional integrated circuits’, IET Comput. Digit. Tech., 2017, 11, (5), pp. 190196.
    6. 6)
      • 6. Viswanath, R., Wakharkar, V., Watwe, A., et al: ‘Thermal performance challenges from silicon to systems’, Intel Technol. J., 2000, 4, (3), pp. 116.
    7. 7)
      • 7. Ge, Y., Malani, P., Qiu, Q.: ‘Distributed task migration for thermal management in many-core systems’. Design Automation Conf. (DAC), Anaheim, USA, 2010, pp. 579584.
    8. 8)
      • 8. Sharifi, S., Ayoub, R., Rosing, T.S.: ‘TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs’. The Conf. on Design, Automation and Test in Europe (DATE), Dresden, Germany, 2012, pp. 593598.
    9. 9)
      • 9. Libutti, S., Massari, G., Fornaciar, W.: ‘Co-scheduling tasks on multi-core heterogeneous systems: an energy-aware perspective’, IET Comput. Digit. Tech., 2016, 10, (2), pp. 7784.
    10. 10)
      • 10. Xie, Y., Hung, W.L.: ‘Temperature-aware task allocation and scheduling for embedded multiprocessor systems-on-chip (MPSoC) design’, J. VLSI Signal Process. Syst. Signal, Image Video Technol., 2006, 45, (3), pp. 177189.
    11. 11)
      • 11. Mulas, F., Pittau, M., Buttu, M., et al: ‘Thermal balancing policy for streaming computing on multiprocessor architectures’. The Conf. on Design, Automation and Test in Europe (DATE), Munich, Germany, 2008, pp. 734739.
    12. 12)
      • 12. Massi, G., Morganti, G., Claudi, A., et al: ‘A methodological approach to fully automated highly accelerated life tests’, Microsyst. Technol., 2016, 22, (6), pp. 111.
    13. 13)
      • 13. Tsai, T., Chen, Y.: ‘Thermal-throttling server: a thermal-aware real-time task scheduling framework for three-dimensional multicore chips’, J. Syst. Softw., 2016, 112, (1), pp. 1125.
    14. 14)
      • 14. Xu, S., Koren, I., Krishna, C.: ‘Thermal-aware task allocation and scheduling for heterogeneous multi-core cyber-physical systems’. Int. Conf. on Embedded Systems, Cyber-physical Systems, and Applications (ESCS'16), Las Vegas, USA, 2016, pp. 1016.
    15. 15)
      • 15. Chu, H., Kao, Y., Chen, Y.: ‘Adaptive thermal-aware task scheduling for multi-core systems’, J. Syst. Softw., 2015, 99, (1), pp. 155174.
    16. 16)
      • 16. Salamy, H.: ‘An effective approach to schedule time reduction on multi-core embedded systems’, Comput. Electr. Eng., 2017, 64, (1), pp. 1533.
    17. 17)
      • 17. Zhou, J., Cao, K., Cong, P., et al: ‘Reliability and temperature constrained task scheduling for makespan minimization on heterogeneous multi-core platforms’, J. Syst. Softw., 2017, 133, (1), pp. 116.
    18. 18)
      • 18. Coskun, A.K., Rosing, T.S., Gross, K.C.: ‘Temperature management in multiprocessor SoCs using online learning’. Design Automation Conf. (DAC), Anaheim, USA, 2008, pp. 890893.
    19. 19)
      • 19. Coskun, A.K., Rosing, T.S., Whisnant, K.A., et al: ‘Temperature-aware MPSoC scheduling for reducing hot spots and gradients’. The Asia and South Pacific Design Automation Conf. (ASP-DAC), Seoul, Korea, 2008, pp. 4954.
    20. 20)
      • 20. Lee, J.G., Kwak, S.: ‘A performance-aware yield analysis and optimization of many core architectures’, Comput. Electr. Eng., 2016, 54, (1), pp. 4052.
    21. 21)
      • 21. Kondo, M., Kobyashi, H., Sakamoto, R., et al: ‘Design and evaluation of fine-grained power-gating for embedded microprocessors’. The Conf. on Design, Automation and Test in Europe (DATE), Dresden, Germany, 2014, pp. 145:1145:6.
    22. 22)
      • 22. Zhang, Y., Duan, L., Li, B., et al: ‘Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors’. Int. Symp. on Quality Electronic Design (ISQED), Santa Clara, USA, 2014, pp. 660666.
    23. 23)
      • 23. Sheikh, H.F., Ahmad, I., Fan, D.: ‘An evolutionary technique for performance-energy-temperature optimized scheduling of parallel tasks on multi-core processors’, IEEE Trans. Parallel Distrib. Syst., 2016, 27, (3), pp. 668681.
    24. 24)
      • 24. Iranfar, A., Kamal, M., Afzali-Kusha, A., et al: ‘The spot: thermal stress-aware power and temperature management for multiprocessor systems-on-chip’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2018, 37, (8), pp. 15321545.
    25. 25)
      • 25. Wang, H., Ma, J., Tan, S.X.D., et al: ‘Hierarchical dynamic thermal management method for high-performance many-core microprocessors’, ACM Trans. Des. Autom. Electron. Syst. (TODAES), 2016, 22, (1), p. 1.
    26. 26)
      • 26. Sharifi, S., Rosing, T.Š.: ‘Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management’, IEEE Trans. Comput.- Aided Des. Integr. Circuits Syst., 2010, 29, (10), pp. 15861599.
    27. 27)
      • 27. Cochran, R., Reda, S.: ‘Thermal prediction and adaptive control through workload phase detection’, ACM Trans. Des. Autom. Electron. Syst. (TODAES), 2013, 18, (1), p. 7.
    28. 28)
      • 28. Zapater, M., Tuncer, O., Ayala, J.L., et al: ‘Leakage-aware cooling management for improving server energy efficiency’, IEEE Trans. Parallel Distrib. Syst., 2015, 26, (10), pp. 27642777.
    29. 29)
      • 29. Liao, C.H., Wen, C.H., Chakrabarty, K.: ‘An online thermal-constrained task scheduler for 3D multi-core processors’. The Conf. on Design, Automation and Test in Europe (DATE), Grenoble, France, 2015, pp. 351356.
    30. 30)
      • 30. Egilmez, B., Memik, G., Ogrenci-Memik, S., et al: ‘User-specific skin temperature-aware DVFS for smartphones’. The Conf. on Design, Automation and Test in Europe (DATE), Grenoble, France, 2015, pp. 12171220.
    31. 31)
      • 31. Das, A., Kumar, A., Veeravalli, B.: ‘Temperature aware energy-reliability tradeoffs for mapping of throughput-constrained applications on multimedia MPSoCs’. The Conf. on Design, Automation and Test in Europe (DATE), Dresden, Germany, 2014, pp. 16.
    32. 32)
      • 32. Jung, H., Pedram, M.: ‘Stochastic dynamic thermal management: a Markovian decision-based approach’. Int. Conf. on Computer Design (ICCD), San Jose, USA, 2007, pp. 452457.
    33. 33)
      • 33. Bhat, G., Singla, G., Unver, A.K., et al: ‘Algorithmic optimization of thermal and power management for heterogeneous mobile platforms’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2018, 26, (3), pp. 544557.
    34. 34)
      • 34. Mohaqeqi, M., Kargahi, M., Fouladi, K.: ‘Stochastic thermal control of a multicore real-time system’. Int. Conf. on Parallel, Distributed, and Network-Based Processing (PDP), Heraklion, Greece, 2016, pp. 208215.
    35. 35)
      • 35. Trivedi, K.S., Bobbio, A.: ‘Reliability and availability engineering modeling, analysis, and applications’ (Cambridge University Press, Cambridge, UK, 2017, 1st edn.).
    36. 36)
      • 36. Bolch, G., Greiner, S., Meer, H.D., et al: ‘Queueing networks and Markov chains’ (John Wiley & Sons, Hoboken, NJ, USA, 2006, 2nd edn.).
    37. 37)
      • 37. Trivedi, K.S., Muppala, J.K., Woolet, S.P., et al: ‘Composite performance and dependability analysis’, Perform. Eval., 1992, 14, (2–3), pp. 197215.
    38. 38)
      • 38. Entezari-Maleki, R., Mohammadkhan, A., Yeom, H.Y., et al: ‘Combined performance and availability analysis of distributed resources in grid computing’, J. Supercomput., 2014, 69, (2), pp. 827844.
    39. 39)
      • 39. Zhou, J., Wei, T., Chen, M., et al: ‘Thermal-aware task scheduling for energy minimization in heterogeneous real-time MPSoC systems’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2016, 35, (8), pp. 12691282.
    40. 40)
      • 40. Wang, S., Bettati, R.: ‘Delay analysis in temperature-constrained hard real-time systems with general task arrivals’. Int. Real-Time Systems Symp. (RTSS), Rio de Janeiro, Brazil, 2006, pp. 323334.
    41. 41)
      • 41. Jayaseelan, R., Mitra, T.: ‘Temperature aware task sequencing and voltage scaling’. Int. Conf. on Computer-Aided Design, San Jose, California, 2008, pp. 618623.
    42. 42)
      • 42. Bini, E., Buttazzo, G., Eker, J., et al: ‘Resource management on multicore systems: the ACTORS approach’, IEEE Micro, 2011, 31, (3), pp. 7281.
    43. 43)
      • 43. Madan, N., Buyuktosunoglu, A., Bose, P., et al: ‘A case for guarded power gating for multi-core processors’. Int. Symp. on High Performance Computer Architecture (HPCA), Washington, USA, 2011, pp. 291300.
    44. 44)
      • 44. Mariani, G., Palermo, G., Silvano, C., et al: ‘Arte: an application-specific run-time management framework for multi-core systems’. Symp. on Application Specific Processors (SASP), Washington, USA, 2011, pp. 8693.
    45. 45)
      • 45. Standard Performance Evaluation Corporation. SPEC CPU benchmark suite. Available at http://www.specbench.org/osg/cpu2006/ [Accessed on June 2018]..
    46. 46)
      • 46. Bienia, C., Kumar, S., Li, K.: ‘Parsec vs. Splash-2: a quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors’. Int. Symp. on Workload Characterization, Seattle, WA, 2008, pp. 4756.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2018.5131
Loading

Related content

content/journals/10.1049/iet-cdt.2018.5131
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address