access icon free Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs

Most of prior hardware Trojan detection approaches require golden chips for references. A classification-based golden chips-free hardware Trojan detection technique has been proposed in the authors’ previous work. However, the algorithm in that work is trained by simulated ICs without considering a shift between the simulation and silicon fabrication. In this study, a co-training based hardware Trojan detection method by exploiting inaccurate simulation models and unlabeled fabricated ICs is proposed to provide reliable detection capability when facing fabricated ICs, which eliminates the need of golden chips. Two classification algorithms are trained using simulated ICs. These two algorithms can identify different patterns in the unlabelled ICs during test-time, and thus can label some of these ICs for the further training of the other algorithm. Moreover, a statistical examination is used to choose ICs labelling for the other algorithm. A statistical confidence interval based technique is also used to combine the hypotheses of the two classification algorithms. Furthermore, the partial least squares method is used to preprocess the raw data of ICs for feature selection. Both EDA experiment results and field programmable gate array (FPGA) experiment results show that the proposed technique can detect unknown Trojans with high accuracy and recall.

Inspec keywords: invasive software; pattern classification; field programmable gate arrays; electronic design automation; embedded systems

Other keywords: unlabelled ICs; reliable detection capability; authors; unknown Trojans; IC; prior hardware Trojan detection approaches; final detection decision; accurate hardware Trojan detection technique; Hardware Trojans; electronic design automation simulation; simulated ICs; statistical confidence interval based technique; detection performance; silicon fabrication; classification-based golden chips-free hardware Trojan detection technique; integrated circuit industry; labelled ICs; inaccurate simulation models; fabricated ICs; ICs labelling; inaccurate simulated models; co-training based hardware Trojan detection method; classification algorithm; co-training method

Subjects: Logic circuits; Logic and switching circuits; Other topics in statistics; Data security

References

    1. 1)
      • 5. Huang, Y., Bhunia, S., Mishra, P.: ‘Scalable test generation for Trojan detection using side channel analysis’, IEEE Trans. Inf. Forensics Sec., 2018, 13, (11), pp. 27462760.
    2. 2)
      • 26. http://www.xilinx.com/products/design-tools/vivado.html.
    3. 3)
      • 22. Bennett, K.P., Embrechts, M.J.: ‘An optimization perspective on kernel partial least squares regression’, Adv. Learn. Theory, Methods Models Appl., 2003, 3, (10), pp. 227250.
    4. 4)
      • 11. Yoshimizu, N.: ‘Hardware Trojan detection by symmetry breaking in path delays’. Int. Symp. on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, May 2014, pp. 107111.
    5. 5)
      • 18. Xue, M., Bian, R., Wang, J., et al: ‘A co-training based hardware Trojan detection technique by exploiting unlabeled ICs and inaccurate simulation models’. The 17th IEEE Int. Conf. on Trust, Security And Privacy In Computing And Communications (TrustCom-18), New York, USA, July 2018, pp. 14521457.
    6. 6)
      • 3. Nowroz, A.N., Hu, K., Koushanfar, F., et al: ‘Novel techniques for high-sensitivity hardware Trojan detection using thermal and power maps’. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2014, 33, (12), pp. 17921805.
    7. 7)
      • 6. Lamech, C., Plusquellic, J.: ‘Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure’. Proc. of the Int. Symp. on Hardware-Oriented Security and Trust (HOST), San Francisco, USA, June 2012, pp. 7582.
    8. 8)
      • 1. Chakraborty, R.S., Wolff, F., Paul, S., et al: ‘MERO: a statistical approach for hardware Trojan detection’. Workshop on Cryptographic Hardware and Embedded Systems (CHES), Lausanne, Switzerland, September 2009, pp. 396410.
    9. 9)
      • 10. Zheng, Y., Yang, S., Bhunia, S.: ‘SeMIA: self-similarity based IC integrity analysis’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2016, 35, (1), pp. 3748.
    10. 10)
      • 25. Reece, T., Robinson, W.H.: ‘Analysis of data-leak hardware Trojans in AES cryptographic circuits’. IEEE Int. Conf. on Technologies for Homeland Security (HST), Waltham, MA, USA, November 2013, pp. 467472.
    11. 11)
      • 7. Wu, T.F., Ganesan, K., Hu, Y.A., et al: ‘TPAD: hardware Trojan prevention and detection for trusted integrated circuits’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2016, 35, (4), pp. 521534.
    12. 12)
      • 15. Kulkarni, A., Pino, Y., Mohsenin, T.: ‘SVM-based real-time hardware Trojan detection for many-core platform’. Int. Symp. on Quality Electronic Design, Santa Clara, CA, USA, March 2016, pp. 362367.
    13. 13)
      • 14. Bao, C., Forte, D., Srivastava, A.: ‘On reverse engineering-based hardware Trojan detection’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2016, 35, (1), pp. 4957.
    14. 14)
      • 24. Daemen, J., Rijmen, V.: ‘The design of Rijndael: AES – the advanced encryption standard’ (Springer press, Berlin, 2002, 1st edn.).
    15. 15)
      • 16. Kulkarni, A., Pino, Y., Mohsenin, T.: ‘Adaptive realtime Trojan detection framework through machine learning’. IEEE Int. Symp. on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, May 2016, pp. 120123.
    16. 16)
      • 12. Nasr, A.A., Abdulmageed, M.Z.: ‘Automatic feature selection of hardware layout: a step toward robust hardware Trojan detection’, J. Electron. Test., 2016, 32, pp. 357367.
    17. 17)
      • 23. Rosipal, R., Trejo, L.J.: ‘Kernel partial least squares regression in reproducing kernel Hilbert space’, J. Mach. Learn. Res., 2001, 2, (2), pp. 97123.
    18. 18)
      • 17. Xue, M., Wang, J., Hu, A.: ‘An enhanced classification-based golden chips-free hardware Trojan detection technique’. IEEE Asian Hardware Oriented Security and Trust Symp. (AsianHOST), Taiwan, December 2016, pp. 16.
    19. 19)
      • 13. Bao, C., Forte, D., Srivastava, A.: ‘On application of one-class SVM to reverse engineering-based hardware Trojan detection’. 15th Int. Symp. on Quality Electronic Design, Santa Clara, CA, USA, March 2014, pp. 4754.
    20. 20)
      • 8. Xiao, K., Forte, D., Tehranipoor, M.: ‘A novel built-in self-authentication technique to prevent inserting hardware Trojans’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2014, 33, (12), pp. 17781791.
    21. 21)
      • 19. http://www.trust-hub.org/.
    22. 22)
      • 2. Agrawal, D., Baktir, S., Karakoyunlu, D., et al: ‘Trojan detection using IC fingerprinting’. Proc. of IEEE Symp. on Security and Privacy (SP), Oakland, California, USA, May 2007, pp. 296310.
    23. 23)
      • 4. Huang, Y., Bhunia, S., Mishra, P.: ‘MERS: statistical test generation for side-channel analysis based Trojan detection’. Proc. of ACM SIGSAC Conf. on Computer and Communications Security (CCS), Vienna, Austria, October 2016, pp. 130141.
    24. 24)
      • 9. Narasimhan, S., Wang, X., Du, D., et al: ‘TeSR: a robust temporal self-referencing approach for hardware Trojan detection’. Proc. of the 4th Int. Symp. on Hardware-Oriented Security and Trust (HOST), San Diego, California, USA, June 2011, pp. 7174.
    25. 25)
      • 21. Angluin, D., Laird, P.: ‘Learning from noisy examples’, Mach. Learn., 1988, 2, (4), pp. 343370.
    26. 26)
      • 20. Goldman, S., Zhou, Y.: ‘Enhancing supervised learning with unlabeled data’. Proc. of the Seventeenth Int. Conf. on Machine Learning (ICML), Stanford, CA, USA, June–July 2000, pp. 327334.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2018.5120
Loading

Related content

content/journals/10.1049/iet-cdt.2018.5120
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading