access icon free An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging.

Inspec keywords: three-dimensional integrated circuits; clocks; buffer circuits; trees (mathematics); VLSI; integrated circuit design

Other keywords: Elmore delay method; dynamic power consumption; 3D IC clock tree design algorithm; multiple TSVs; obstacle avoiding abstract clock tree; chip performance; through-silicon-vias; clock skew; obstacle-avoiding clock routing tree construction; effective clock tree design; clock network

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Combinatorial mathematics; Other digital circuits

References

    1. 1)
      • 1. Lu, T., Srivastava, A.: ‘Low-power clock tree synthesis for 3D-ICs’, ACM Trans. Des. Autom. Electron. Syst., 2017, 22, pp. 50:150:24.
    2. 2)
      • 13. Lu, T., Srivastava, A.: ‘Gated low-power clock tree synthesis for 3D-ICs’. 2014 IEEE/ACM Int. Symp. on Low Power Electronics and Design (ISLPED), La Jolla, CA, USA, August 2014, pp. 319322.
    3. 3)
      • 17. Chen, X., Zhu, T., Davis, W.R., et al: ‘Adaptive and reliable clock distribution design for 3-D integrated circuits’, IEEE Trans. Compon. Packag. Manuf. Technol., 2014, 4, pp. 18621870.
    4. 4)
      • 21. Chen, Y.C., Hsu, C.C., Lin, M.P.H.: ‘Low-power gated clock tree optimization for three-dimensional integrated circuits’. VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2015, pp. 14.
    5. 5)
      • 4. Nagendra, C., Irwin, M.J., Owens, R.M.: ‘Area-time-power tradeoffs in parallel adders’, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 1996, 43, (10), pp. 689702.
    6. 6)
      • 7. Zhao, X., Lim, S.K.: ‘Power and slew-aware clock network design for through silicon-via (TSV) based 3D ICs’. 2010 15th Asia and South Pacific Design Automation Conf. (ASP-DAC), Taipei, Taiwan, January 2010, pp. 175180.
    7. 7)
      • 5. Zhu, Q.K.: ‘High-speed clock network design’ (Kluwer Academic Publishers, Boston, MA, USA, 2003).
    8. 8)
      • 31. Cormen, T.H.: ‘Introduction to algorithms’ (MIT press, Cambridge, Massachusetts, 2009).
    9. 9)
      • 23. Lin, M., Sun, H., Kimura, S.: ‘Power-efficient and slew-aware three dimensional gated clock tree synthesis’. 2016 IFIP/IEEE Int. Conf. on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, September 2016, pp. 16.
    10. 10)
      • 18. Liu, W., Du, H., Wang, Y., et al: ‘TSV-aware topology generation for 3D clock tree synthesis’. Int. Symp. on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 2013, pp. 300307.
    11. 11)
      • 6. Dong, X., Xie, Y.: ‘System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)’. 2009 Asia and South Pacific Design Automation Conf., Yokohama, Japan, January 2009, pp. 234241.
    12. 12)
      • 25. Ahmed, N., Tehranipour, M.H., Zhou, D., et al: ‘Frequency driven repeater insertion for deep submicron’. 2004 IEEE Int. Symp. on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada, May 2004, vol. 5, pp. V181–V–184.
    13. 13)
      • 11. Minz, J., Zhao, X., Lim, S.K.: ‘Buffered clock tree synthesis for 3D ICs under thermal variations’. 2008 Asia and South Pacific Design Automation Conf., Seoul, Republic of Korea, March 2008, pp. 504509.
    14. 14)
      • 27. Gambino, J.P., Adderly, S.A., Knickerbocker, J.U.: ‘An overview of through-silicon-via technology and manufacturing challenges’, Microelectron. Eng., 2015, 135, pp. 73106.
    15. 15)
      • 12. Yang, Y.: ‘Three-dimensional pipeline clock network design with multi-layer processor chip and multi-clock VLSI system’. 2013 Int. SoC Design Conf. (ISOCC), Busan, Republic of Korea, November 2013, pp. 019022.
    16. 16)
      • 9. Shelar, R.S., Patyra, M.: ‘Impact of local interconnects on timing and power in a high performance microprocessor’. Proc. of the 19th Int. Symp. on Physical Design, ISPD ‘10, New York, NY, USA, 2010, pp. 145152.
    17. 17)
      • 14. Navidi, M.M., Byun, G.S.: ‘Comparative analysis of clock distribution networks for TSV-based 3D IC designs’. Fifteenth Int. Symp. on Quality Electronic Design, Santa Clara, CA, USA, March 2014, pp. 184188.
    18. 18)
      • 3. Sturgeon, T., Kawakami, M.: ‘Global value chains in the electronics industry: was the crisis a window of opportunity for developing countries?’, 2010.
    19. 19)
      • 2. Zhao, X., Minz, J., Lim, S.K.: ‘Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs’, IEEE Trans. Compon. Packag. Manuf. Technol., 2011, 1, pp. 247259.
    20. 20)
      • 30. ISPD: ‘ISPD'10 CNS contest’, 2010. Available at http://www.sigda.org/ispd/contests/10/ispd10cns.html.
    21. 21)
      • 24. Kim, D.H., Lim, S.K.: ‘Impact of TSV and device scaling on the quality of 3D ICs’ (Springer New York, New York, NY, 2015), pp. 122.
    22. 22)
      • 19. Yang, J.-S., Pak, J., Zhao, X., et al: ‘Robust clock tree synthesis with timing yield optimization for 3D-ICs’. Proc. of the 16th Asia and South Pacific Design Automation Conf., ASPDAC ‘11, Piscataway, NJ, USA, 2011, pp. 621626.
    23. 23)
      • 10. Kim, T.Y., Kim, T.: ‘Clock tree synthesis with pre-bond testability for 3D stacked IC designs’. Design Automation Conf., Anaheim, CA, USA, June 2010, pp. 723728.
    24. 24)
      • 22. Pan, X., Xie, J., Wang, Q., et al: ‘Noise aware clock tree synthesis for 3D ICs’. 2014 12th IEEE Int. Conf. on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, October 2014, pp. 13.
    25. 25)
      • 15. Zhao, X., Lim, S.K.: ‘Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs’. 17th Asia and South Pacific Design Automation Conf., Sydney, NSW, Australia, January 2012, pp. 347352.
    26. 26)
      • 26. Deschacht, D.: ‘Optimum repeater insertion to minimize the propagation delay into 32 nm RLC interconnect’. 2011 IEEE Electrical Design of Advanced Packaging and Systems Symp. (EDAPS), Hanzhou, China, 2011, pp. 14.
    27. 27)
      • 29. ISPD: ‘ISPD bench mark’, 2009. Available at http://www.sigda.org/ispd/contests/ispd09cts.html.
    28. 28)
      • 20. Wang, S.J., Lin, C.H., Li, K.S.M.: ‘Synthesis of 3D clock tree with pre-bond testability’. 2013 IEEE Int. Symp. on Circuits and Systems (ISCAS2013), Beijing, China, May 2013, pp. 26542657.
    29. 29)
      • 16. Chen, F.W., Hwang, T.: ‘Clock tree synthesis with methodology of re-use in 3D IC’. DAC Design Automation Conf. 2012, San Francisco, CA, USA, June 2012, pp. 10941099.
    30. 30)
      • 8. Kim, T.-Y., Kim, T.: ‘Clock tree synthesis for TSV-based 3D IC designs’, ACM Trans. Des. Autom. Electron. Syst., 2011, 16, pp. 48:148:21.
    31. 31)
      • 28. I. 2010: ‘International technology roadmap for semiconductors’, 2010. Available at http://www.itrs.net/.
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