Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits

Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Hardware Trojan (HT), which usually is activated under rare conditions associated with low transition bits in a circuit, can lead to circuit functional failure or information leakage. Effectively activating hidden HTs is a major challenge during the HT detection process. In this study, the authors propose a novel approach for efficiently activating Trojans hidden in digital signal processing (DSP) circuits by increasing the transition activity of rare bits. In particular, the bit-level transition activity can be increased by controlling signal word-level statistical properties, such as standard deviation and autocorrelation, and their propagation through various operators involved in DSP circuit design. As a result, the proposed approach can generate appropriate test vectors, which effectively activate internal rare nodes and trigger HTs. The experimental results show that using the proposed approach the transition activity of rare bits is significantly increased and various HTs inserted into DSP circuits are activated with reduced time. By comparing to an existing activation approach working at the bit level, the proposed approach is superior in test vectors generation time up to 9 times reduction and HT activation time up to 66 times reduction.

Related content

This is a required field
Please enter a valid email address