access icon free Throughput/area optimised pipelined architecture for elliptic curve crypto processor

© The Institution of Engineering and Technology
Received 25/04/2018, Accepted 26/02/2019, Revised 17/11/2018, Published 26/02/2019

A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

Inspec keywords: field programmable gate arrays; public key cryptography; pipeline processing; digital arithmetic

Other keywords: word length 283.0 bit; point doubling; throughput/area optimised pipelined architecture; FPGA; point multiplication computation; word length 233.0 bit; frequency 337.0 MHz; critical path delay; frequency 357.0 MHz; word length 163.0 bit; throughput/area ratio; elliptic curve cryptography; area overhead; elliptic curve crypto processor; arithmetic unit; point addition; clock cycles; frequency 369.0 MHz

Subjects: Logic circuits; Security aspects of hardware; Logic and switching circuits; Multiprocessing systems; Digital arithmetic methods; Parallel architecture; Cryptography

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