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Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

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A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.


    1. 1)
      • 8. Liu, S., Ju, L., Cai, X., et al: ‘High performance FPGA implementation of elliptic curve cryptography over binary fields’. 2014 IEEE 13th Int. Conf. on Trust, Security and Privacy in Computing and Communications (TrustCom), Beijing, China, 2014, pp. 148155.
    2. 2)
      • 22. Hankerson, D., Menezes, A., Vanstone, S.: ‘Guide to elliptic curve cryptography’ (Springer-Verlag, New York, 2004, 1st edn.), pp. 1311.
    3. 3)
      • 17. Jumaa, N.K.: ‘Survey: internet of thing using FPGA’, Iraq J. Electr. Electron. Eng., 2017, 13, (1), pp. 3845.
    4. 4)
      • 10. Khan, Z.U.A., Benaissa, M.: ‘High speed ECC implementation on FPGA over GF(2m)’. IEEE Proc. of 25th Int. Conf. on Field-Programmable Logic Applications, London, UK, 2015, pp. 16.
    5. 5)
      • 14. Imran, M., Kashif, M., Rashid, M.: ‘Hardware design and implementation of scalar multiplication in elliptic curve cryptography (ECC) over GF(2163) on FPGA’. IEEE Proc. of 6th Int. Conf. on Information and Communication Technologies (ICICT), Karachi, Pakistan, December 2015, pp. 14.
    6. 6)
      • 13. Nguyen, T.T., Lee, H.: ‘Efficient algorithm and architecture for elliptic curve cryptographic processor’, J. Semicond. Technol. Sci., 2016, 16, (1), pp. 118125.
    7. 7)
      • 25. Itoh, T., Tsujii, S.: ‘A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases’, J. Inf. Comput., 1988, 78, (3), pp. 171177.
    8. 8)
      • 6. Zhang, Y., Chen, D., Choi, Y., et al: ‘A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)’, Microprocess. Microsyst., 2010, 34, pp. 228236.
    9. 9)
      • 7. Mahdizadeh, H., Masoumi, M.: ‘Novel architecture for efficient FPGA implementation of elliptic curve cryptographic processor over GF(2163)’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (12), pp. 23302333.
    10. 10)
      • 1. Rivest, R.L., Shamir, A., Adleman, L.: ‘A method for obtaining digital signatures and public-key cryptosystems’, Commun. ACM, 1978, 21, (2), pp. 120126.
    11. 11)
      • 9. Azarderakhsh, R., Reyhani-Masoleh, A.: ‘Efficient FPGA implementations of point multiplication on binary Edwards and generalized Hessian curves using Gaussian normal basis’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (8), pp. 14531466.
    12. 12)
      • 3. National Institute of Standards and Technology (NIST): ‘Recommended elliptic curves for federal government use’, July 1999. Available at, accessed April 2018.
    13. 13)
      • 11. Khan, Z.U.A., Benaissa, M.: ‘High-speed and low-latency ECC processor implementation over GF(2m) on FPGA’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (1), pp. 165176.
    14. 14)
      • 15. Imran, M., Shafi, I., Jafri, A.R., et al: ‘Hardware design and implementation of ECC based crypto processor for low-area-applications on FPGA’. IEEE Proc. of 11th Int. Conf. on Open Source Systems and Technologies (ICOSST), Lahore, Pakistan, December 2017, pp. 5459.
    15. 15)
      • 20. Rashid, M., Imran, M., Jafri, A.R., et al: ‘Flexible architectures for cryptographic algorithms- a systematic literature review’, J. Circuits Syst. Comput., 2019, 28, pp. 1930003-11930003-35.
    16. 16)
      • 12. Roy, S.S., Rebeiro, C., Mukhopadhyay, D.: ‘Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (5), pp. 901909.
    17. 17)
      • 2. Koblitz, N.: ‘Elliptic curve cryptosystems’, Math. Comput., 1987, 48, (177), pp. 203209.
    18. 18)
      • 24. Imran, M., Rashid, M.: ‘Architectural review of polynomial bases finite field multipliers over GF(2m)’. IEEE Int. Conf. on Communication, Computing and Digital Systems (C-CODE), Islamabad, Pakistan, May 2017, pp. 331336.
    19. 19)
      • 16. Shafique, M., Theocharides, T., Bouganis, C., et al: ‘An overview of next-generation architectures for machine learning: roadmap, opportunities and challenges in the IoT era’. Proc. of DATE Conf., Dresden, Germany, 2018, pp. 827832.
    20. 20)
      • 5. Kim, C.H., Kwon, S., Hong, C.P.: ‘FPGA implementation of high performance elliptic curve cryptographic processor over GF(2163)’, J. Syst. Archit., 2008, 54, (10), pp. 893900.
    21. 21)
      • 21. Jafri, A.R., Islam, M.N., Imran, M., et al: ‘Towards an optimized architecture for unified binary huff curves’, J. Circuits Syst. Comput., 2017, 26, (11), pp. 114.
    22. 22)
      • 23. Montgomery, P.L.: ‘Speeding the pollard and elliptic curve methods of factorization’, Math. Comput., 1987, 48, (177), pp. 243264.
    23. 23)
      • 19. Rashidi, B., Sayedi, S.M., Reza, F.R.: ‘High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems’, Microelectron. J., 2016, 52, pp. 4965.
    24. 24)
      • 4. Chelton, W.N., Benaissa, M.: ‘Fast elliptic curve cryptography on FPGA’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2008, 16, (2), pp. 198205.
    25. 25)
      • 18. Sareen, P.: ‘Cloud computing: types, architecture, applications, concerns, virtualization and role of IT governance in cloud’, Int. J. Adv. Res. Comput. Sci. Softw. Eng., 2013, 3, (3), pp. 533538.

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