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Power-efficient reliable register file for aggressive-environment applications

Power-efficient reliable register file for aggressive-environment applications

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In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors’ results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.

References

    1. 1)
      • 1. Reviriego, P., Maestro, J.A., Flanagan, M.F.: ‘Error detection in majority logic decoding of Euclidean geometry low density parity check (eg-ldpc) codes’, IEEE Trans. VLSI Syst., 2013, 21, pp. 156159.
    2. 2)
      • 2. Guena, P.: ‘A cache primer’, Application Note Freescale Semiconductor, 2004.
    3. 3)
      • 3. Gherman, V., Evain, S., Seymour, N., et al: ‘Generalized parity-check matrices for sec-ded codes with fixed parity’. 2011 IEEE 17th Int. On-Line Testing Symp. (IOLTS), Athens, Greece, 2011, pp. 198201.
    4. 4)
      • 4. Ahangari, H., Alouani, I., Ozturk, O., et al: ‘Register file reliability enhancement through adjacent narrow-width exploitation’. Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era (DTIS 2016), Istanbul, Turkey, 2016, vol. 35.
    5. 5)
      • 5. ‘European Space Agency, ERC32’. Available at http://microelectronics.esa.int/erc32/index.html.
    6. 6)
      • 6. Gaisler, J.: ‘A portable and fault-tolerant microprocessor based on the sparc v8 architecture’. Proc. Int. Conf. on Dependable Systems and Networks, Washington, DC, USA, 2002, pp. 409415.
    7. 7)
      • 7. Villalpando, C., Rennels, D., Some, R., et al: ‘Reliable multicore processors for nasa space missions’. 2011 Aerospace Conf., Big Sky, MT, USA, 2011, pp. 112.
    8. 8)
      • 8. Memik, G., Kandemir, M.T., Ozturk, O.: ‘Increasing register file immunity to transient errors’. Design, Automation and Test in Europe, Munich, Germany, 2005, vol. 1, pp. 586591.
    9. 9)
      • 9. Hu, J., Wang, S., Ziavras, S.G.: ‘On the exploitation of narrow-width values for improving register file reliability’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2009, 17, (7), pp. 953963.
    10. 10)
      • 10. Kandala, M., Zhang, W., Yang, L.T.: ‘An area-efficient approach to improving register file reliability against transient errors’. 21st Int. Conf. on Advanced Information Networking and ApplicationsWorkshops, 2007 (AINAW'07), Niagara Falls, Canada, 2007, vol. 1, pp. 798803.
    11. 11)
      • 11. Shin, D., Gupta, S.K.: ‘Approximate logic synthesis for error tolerant applications’. 2010 Design, Automation Test in Europe Conf. Exhibition (DATE 2010), Dresden, Germany, 2010, pp. 957960.
    12. 12)
      • 12. Fujiwara, H., Okumura, S., Iguchi, Y., et al: ‘Quality of a bit (qob): A new concept in dependable sram’. 9th Int. Symp. on Quality Electronic Design (isqed 2008), San Jose, CA, USA, 2008, pp. 98102.
    13. 13)
      • 13. Ahangari, H., Yalcin, G., Ozturk, O., et al: ‘Jsram: A circuit-level technique for trading-off robustness and capacity in cache memories’. IEEE Computer Society Annual Symp. on VLSI, Montpellier, France, 2015, pp. 149154.
    14. 14)
      • 14. Li, X., Yeung, D.: ‘Application-level correctness and its impact on fault tolerance’. 2007 IEEE 13th Int. Symp. on High Performance Computer Architecture, Phoenix, AZ, USA, 2007, pp. 181192.
    15. 15)
      • 15. Misailovic, S., Sidiroglou, S., Hoffmann, H., et al: ‘Quality of service profiling’. Proc. of the 32Nd ACM/IEEE Int. Conf. on Software Engineering (ICSE ‘10), New York, NY, USA, 2010, vol. 1, pp. 2534.
    16. 16)
      • 16. Fujiwara, H., Okumura, S., Iguchi, Y., et al: ‘A 7t/14t dependable sram and its array structure to avoid half selection’. 2009 22nd Int. Conf. on VLSI Design, New Delhi, India, 2009, pp. 295300.
    17. 17)
      • 17. ‘Predictive technology model (ptm) website’. Available at http://www.cfreds.nist.gov/.
    18. 18)
      • 18. C., S., : ‘Advanced MOSFET designs and implications for SRAM scaling’. PhD Thesis, 2011.
    19. 19)
      • 19. Yoshimoto, S., Amashita, T., Okumura, S., et al: ‘Bit error and soft error hardenable 7t/14t sram with 150-nm fd-soi process’. 2011 Int. Reliability Physics Symp., Monterey, CA, USA, 2011, pp. SE.3.1SE.3.6.
    20. 20)
      • 20. Baumann, R.: ‘Soft errors in advanced computer systems’, Des. Test Comput., 2005, 22, (3), pp. 258266.
    21. 21)
      • 21. Austin, T., Larson, E., Ernst, D.: ‘Simplescalar: an infrastructure for computer system modeling’, IEEE Comput., 2002, 35, pp. 5967.
    22. 22)
      • 22. Guthaus, M.R., Ringenberg, J.S., Ernst, D., et al: ‘Mibench: A free, commercially representative embedded benchmark suite’. 2001 IEEE Int. Workshop Proc. of the Workload Characterization 2001 (WWC-4), Austin, TX, USA, 2001.
    23. 23)
      • 23. Neale, A., Jonkman, M., Sachdev, M.: ‘Adjacent-mbu-tolerant sec-ded-taec-yaed codes for embedded srams’, IEEE Trans. Circuits Syst. II, Express Briefs, 2015, 62, (4), pp. 387391.
    24. 24)
      • 24. Koren, I.: ‘Defect and fault tolerance in vlsi systems’, vol. 1, (Springer, New York, NY, USA, 2012).
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