The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR-based circuits can have an over 50% yield advantage over their synchronous counterparts.