%0 Electronic Article %A Yang Zhang %A Ji Li %A Huimei Cheng %A Haipeng Zha %A Jeffrey Draper %A Peter A. Beerel %K bundled data %K delay line %K OR-based circuits %K OR-based clocks %K size 65.0 nm %K process-voltage-temperature variations %K Monte Carlo analysis %K shipped product quality %K mathematical analysis %K ring-oscillator %K bundled-data designs %K combinational logic %X The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR-based circuits can have an over 50% yield advantage over their synchronous counterparts. %@ 1751-8601 %T Yield modelling and analysis of bundled data and ring-oscillator based designs %B IET Computers & Digital Techniques %D May 2019 %V 13 %N 3 %P 262-272 %I Institution of Engineering and Technology %U https://digital-library.theiet.org/;jsessionid=365pganmj9ciq.x-iet-live-01content/journals/10.1049/iet-cdt.2018.5040 %G EN