access icon free Removing constant-induced errors in stochastic circuits

Stochastic computing (SC) computes with probabilities using randomised bit-streams and standard logic circuits. Its major advantages include ultra-low area and power, coupled with high error tolerance. However, due to its randomness features, SC's accuracy is often low and hard to control, thus severely limiting its practical applications. Random fluctuation errors (RFEs) in SC data are a major factor affecting accuracy, and are usually addressed by increasing the bit-stream length N . However, increasing N can result in excessive computation time and energy consumption, counteracting the main advantages of SC. In this work, the authors first observe that many SC designs heavily rely on constant inputs, which contribute significantly to RFEs. They then investigate the role of constant inputs in SC and propose a systematic algorithm constant elimination algorithm for suppression of errors to eliminate the constant-induced RFEs by introducing memory elements into the target circuits. The resulting optimal modulo-counting (OMC) circuits remove all constant inputs and, at the same time, minimise RFEs. Analytical and experimental results are presented demonstrating other aspects of OMC circuits, including their initialisation and autocorrelation properties, as well as their optimality in terms of minimising RFEs.

Inspec keywords: probability; optimisation; counting circuits; logic design; logic circuits; stochastic processes

Other keywords: randomised bit-streams; systematic algorithm constant elimination algorithm; random fluctuation errors; bit-stream length; optimal modulo-counting circuits; stochastic computing; minimise RFEs; constant-inducing RFEs; stochastic circuits; constant-induced errors; OMC circuits; standard logic circuits

Subjects: Optimisation techniques; Logic and switching circuits; Other topics in statistics; Logic circuits; Digital circuit design, modelling and testing; Optimisation techniques; Other topics in statistics; Logic design methods

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2018.5017
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