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access icon free Soft-error reliable architecture for future microprocessors

© The Institution of Engineering and Technology
Received 20/03/2018, Accepted 23/01/2019, Revised 13/01/2019, Published 28/01/2019

The transient error is the failure of the device due to transient hardware faults caused by high-energy particles like neutron and alpha particle strikes. In this study, the authors propose two schemes of fault-tolerant architecture. The first scheme is a hardware-based solution called REMO that combines the best features of space and time redundancy. REMO provides very high fault coverage with minimum overheads in performance, power and area. The second scheme, REMORA combines the best features of hardware and software approaches of fault tolerance. The persistent issue of unprotected code which exists in software approaches is eliminated in this proposal. Simulation results from a SPEC2006 benchmark suite indicate, REMO incurs an increase in the area of about 6%, power overhead is 9% in spite of redundant execution and a negligible performance penalty during a fault-free run. In REMORA, performance degradation increases to 12%. The code size inflation is close to 12%. This is due to the additional signature instructions inserted into the application program. In this study, the authors have explored the possibility of eliminating this penalty by embedding the signatures in control flow instructions. The power and area overhead of REMORA is on par with REMO.

Inspec keywords: fault tolerance; integrated circuit reliability; security of data; redundancy; microprocessor chips; instruction sets; fault tolerant computing

Other keywords: transient hardware faults; fault-free run; negligible performance penalty; high-energy particles; fault tolerance; soft-error reliable architecture; time redundancy; redundant execution; minimum overheads; performance degradation increases; transient error; REMORA; high fault coverage; software approaches; unprotected code; code size inflation; hardware-based solution; REMO; neutron; SPEC2006 benchmark suite; persistent issue; alpha particle strikes; power overhead; future microprocessors; fault-tolerant architecture; simulation results

Subjects: Data security; Microprocessor chips; Reliability; Software engineering techniques; Microprocessors and microcomputers

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