%0 Electronic Article
%A Ahmad A. Alzahrani
%A Ronald F. DeMara
%K reliability exposures
%K reconfigurable hardware devices
%K enhanced timing improvement
%K field programmable gate array toolchain
%K leveraging design diversity
%K time-to-market
%K combined variations
%K diverse implementations
%K modular redundancy methods
%K uncertain parametric variations
%K commercial-grade Xilinx field programmable gate array platform
%K target device
%K increased design complexity
%K performance variation impact
%K process variation
%K graph theory
%K pre-emptive design approach
%K fault resolution space
%K distinct physical implementations
%K largest solution space feasible
%K process parameters
%K relentless scaling
%K reconfiguration-based resilience
%K integrated circuits
%K cost-competitive manufacturability
%K dynamic reconfiguration time
%K reliability degradation
%K interconnect routing constraints
%K union-free hypergraphs
%K optimal designs
%K pervasive computing
%K reliability concerns
%X With continued scaling of integrated circuits into deep nanoscale fabrication technologies, the aggravated effects of reliability degradation and variability in process parameters can hinder effective yields. Fortunately, due to the immense flexibility of contemporary reconfigurable hardware (RH), reconfiguration-based resilience can be exploited to effectively tackle such challenges. Nonetheless, reconfiguration-based resiliency is typically limited due to the complexity of the fault resolution space, interconnect routing constraints, and dynamic reconfiguration time in situ. These challenges are addressed herein by deriving a pre-emptive design approach based on union-free hypergraphs, which can define distinct physical implementations with highly separable subsets of the target device's resources covering the largest solution space feasible for reliability exposures and uncertain parametric variations. Two scalable and highly transportable algorithms to realise union-free hypergraphs are introduced and investigated. Hardware demonstration on a commercial-grade field programmable gate array platform shows a significant increase in fault tolerance compared to commonly-used modular redundancy methods. Furthermore, Monte-Carlo statistical results across a set of benchmarks show an average improvement in critical path delay of 6.8, 8.6, and 10.8% for combined variations of 15, 25, and 35%, respectively, while achieving a net reduction in performance variation impact of 34.8, 38, and 41% for identical levels of variability.
%@ 1751-8601
%T Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ
%B IET Computers & Digital Techniques
%D May 2019
%V 13
%N 3
%P 250-261
%I Institution of Engineering and Technology
%U https://digital-library.theiet.org/;jsessionid=1rjpha0ndq06d.x-iet-live-01content/journals/10.1049/iet-cdt.2018.5012
%G EN