%0 Electronic Article
%A Kollaparampil Somasekharan Sreekala
%A Sukumarapillai Krishnakumar
%K power-delay product
%K state retained dual-voltage threshold feedback sleeper-stack
%K BSIM4 predictive technology model parameters
%K logic circuits
%K low power circuit design
%K exact logic state saving
%K size 45 nm
%K deep submicron technology
%K C17 circuit
%K delay efficient circuit level leakage reduction technique
%K nanoscale devices
%K DSM technology
%K NAND3 gate
%K leakage power reduction
%K leakage power problem
%K FS-S
%X With the advent of nanoscale devices, due to the problems of leakage power has grown enormously. Reducing leakage power is one of the main challenges in the design of low power circuits. This study presents a delay efficient circuit level leakage reduction technique, which uses dual-V th named ‘Feedback Sleeper-Stack (FS-S)’ for deep submicron (DSM) technology. FS-S is proposed in order to reduce leakage power dramatically while saving exact logic state. An analytical RC delay model of the FS-S is derived. Comparisons are then carried out in terms of leakage power, total power, delay, area, and power–delay product to the available leakage reduction techniques. 45 nm BSIM4 Predictive Technology Model parameters are used to estimate the changes in power and delay. FS-S is applied to three generic logic circuits to show that the proposed technique is suitable for general logic circuits. Results show that chain of four inverters, NAND3 gate, and C17 circuit with dual-V th FS-S give 15, 62, and 90% performance levels, respectively, over base case circuit under iso-area condition.
%@ 1751-8601
%T State retained dual-*V* _{th} feedback sleeper-stack for leakage reduction
%B IET Computers & Digital Techniques
%D January 2019
%V 13
%N 1
%P 1-10
%I Institution of Engineering and Technology
%U https://digital-library.theiet.org/;jsessionid=z7u6jirvjo7k.x-iet-live-01content/journals/10.1049/iet-cdt.2018.0009
%G EN