access icon free Synthesis and exploration of clock spines

© The Institution of Engineering and Technology
Received 13/12/2017, Accepted 15/04/2018, Revised 06/04/2018, Published 25/04/2018

This study addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimisation (SFO) problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the SFO. As a result, the authors proposed synthesis algorithm can explore the diverse structures of the clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that the proposed algorithm is able to synthesise the clock spine networks with 38% reduced clock skew over the clock tree structures, even 11% reduced clock power. In addition, in comparison with the clock mesh structures, the proposed clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36%.

Inspec keywords: clock distribution networks; clocks; circuit optimisation; network synthesis

Other keywords: benchmark circuits; SFO problem; reduced clock power; clock spine exploration; slicing floorplan optimisation problem; postfix notation; clock mesh structures; clock spine network structures; clock variation tolerance; for clock spine network synthesis algorithm; fast cost computation; clock resources

Subjects: Other digital circuits; Other circuits for digital computers; Digital circuit design, modelling and testing

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