%0 Electronic Article
%A Youngchan Kim
%A Taewhan Kim
%K fast cost computation
%K benchmark circuits
%K clock mesh structures
%K clock resources
%K clock variation tolerance
%K SFO problem
%K reduced clock power
%K slicing floorplan optimisation problem
%K for clock spine network synthesis algorithm
%K clock spine network structures
%K clock spine exploration
%K postfix notation
%X This study addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimisation (SFO) problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the SFO. As a result, the authors proposed synthesis algorithm can explore the diverse structures of the clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that the proposed algorithm is able to synthesise the clock spine networks with 38% reduced clock skew over the clock tree structures, even 11% reduced clock power. In addition, in comparison with the clock mesh structures, the proposed clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36%.
%@ 1751-8601
%T Synthesis and exploration of clock spines
%B IET Computers & Digital Techniques
%D September 2018
%V 12
%N 5
%P 241-248
%I Institution of Engineering and Technology
%U https://digital-library.theiet.org/;jsessionid=92zgxaa1brja.x-iet-live-01content/journals/10.1049/iet-cdt.2017.0234
%G EN