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access icon free VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors

  • Author(s): Hao Xiao 1 ; Xiang Yin 2 ; Ning Wu 2 ; Xin Chen 2 ; Jun Li 3 ; Xiaoxing Chen 3
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  • Source: Volume 12, Issue 3, May 2018, p. 105 – 110
    DOI:  10.1049/iet-cdt.2017.0060 , Print ISSN 1751-8601, Online ISSN 1751-861X
© The Institution of Engineering and Technology
Received 09/03/2017, Accepted 07/02/2018, Revised 11/12/2017, Published 14/02/2018

Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large-scale integration (VLSI) design of high-precision fixed-point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics-based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area-efficient and high-precision FFT processor, which can perform power-of-two FFT from 32 to 8192 points. By using the SMIC process, the area of the proposed FFT processor is with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192-point FFT at 40 MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the power consumption measured by post-layout simulation is 35.7 mW.

Inspec keywords: optimisation; VLSI; integrated circuit design; statistical analysis; quantisation (signal); fast Fourier transforms; signal denoising

Other keywords: statistics-based optimisation scheme; signal-to-quantisation-noise ratio; quantisation noise; fast Fourier transform; FFT computation; digital signal processing systems; very large-scale integration; scaling approach; VLSI design; low-cost high-precision fixed-point reconfigurable FFT processors

Subjects: Integral transforms; Digital signal processing; Optimisation techniques; Signal processing and detection; Optimisation techniques; Integral transforms; Semiconductor integrated circuit design, layout, modelling and testing; Other topics in statistics; Other topics in statistics

References

    1. 1)
      • 2. Kala, S., Nalesh, S., Nandy, S.K., et al: ‘Energy efficient scalable and dynamically reconfigurable FFT architecture for OFDM system’. 2014 Fifth Int. Symp. Electronic System Design, Mangalore, India, December 2014, pp. 20–24.
    2. 2)
      • 10. Lin, Y.T., Tsai, P.Y., Chiueh, T.D.: ‘Low-power variable-length fast Fourier transform processor’, IEE Proc. Comput. Digit. Tech., 2005, 152, (4), pp. 499–506.
    3. 3)
      • 8. Mario, G., Grajal, J., Sanchez, M.A., et al: ‘Pipelined radix-2k feedforward FFT architectures’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (1), pp. 23–32.
    4. 4)
      • 7. Manohar, A., Michael, B., Keshab, K.P.: ‘Pipelined parallel FFT architectures via folding transformation’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (6), pp. 1068–1081.
    5. 5)
      • 3. Jo, B.G., Sunwoo, M.H.: ‘New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2005, 52, (5), pp. 911–919.
    6. 6)
      • 17. Jian, W., Chunlin, X., Kangli, Z., et al: ‘Fixed-point analysis and parameter optimization of the radix-2k pipelined FFT processor’, IEEE Trans. Signal Process., 2015, 63, (18), pp. 4879–4893.
    7. 7)
      • 11. Chu, Y., Mao-Hsu, Y.: ‘Area-efficient 128- to 2048/1556-point pipeline FFT processor for LTE and mobile WiMAX systems’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2015, 23, (9), pp. 1793–1800.
    8. 8)
      • 15. Sarbishei, O., Radecka, K.: ‘Analysis of mean-square-error (MSE) for fixed-point FFT units’. IEEE Int. Symp. Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 1732–1735.
    9. 9)
      • 9. Song-Nien, T., Chi-Hsiang, L., Tsin-Yuan, C.: ‘An area- and energy-efficient multimode FFT processor for WPAN/WLAN/WMAN systems’, IEEE J. Solid-State Circuits, 2012, 47, (6), pp. 1419–1435.
    10. 10)
      • 5. Baas, B.M.: ‘A low-power, high-performance, 1024-point FFT processor’, IEEE J. Solid-State Circuits, 1999, 34, (3), pp. 380–387.
    11. 11)
      • 14. Wei-Hsin, C., Truong, Q.N.: ‘On the fixed-point accuracy analysis of FFT algorithms’, IEEE Trans. Signal Process., 2008, 56, (10), pp. 4673–4682.
    12. 12)
      • 6. Song-Nien, T., Jui-Wei, T., Tsin-Yuan, C.: ‘A 2.4 GS/s FFT processor for OFDM-based WPAN applications’, IEEE Trans. Circuits Syst. II, Express Briefs, 2010, 57, (6), pp. 451–455.
    13. 13)
      • 16. Mohammad Reza, M., Lesley, S.: ‘Minimizing the error: a study of the implementation of an integer split-radix FFT on an FPGA for medical imaging’. Int. Conf. Field-Programmable Technology, Seoul, Korea (South), December 2012, pp. 360–367.
    14. 14)
      • 19. Manish, S.P., Taral, D.C., Anand, D.D.: ‘An area efficient and low power implementation of 2048 point FFT/IFFT processor for mobile WiMAX’. 2010 Int. Conf. Signal Processing and Communications (SPCOM), Honolulu, USA, July 2010, pp. 1–4.
    15. 15)
      • 4. Pei-Yun, T., Chung-Yi, L.: ‘A generalized conflict-free memory addressing scheme for continuous-flow parallel-processing FFT processors with rescheduling’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2011, 19, (12), pp. 2290–2302.
    16. 16)
      • 13. Anthony, T.J., Dean, N.T., Bevan, M.B.: ‘The design of a reconfigurable continuous-flow mixed-radix FFT processor’. 2009 IEEE Int. Symp. Circuits and Systems, Taipei, Taiwan, May 2009, pp. 1133–1136.
    17. 17)
      • 20. Xiao, H., Pan, A., Chen, Y., et al: ‘Low-cost Reconfigurable VLSI Architecture for Fast Fourier Transform’, IEEE Transaction on Consumer Electronics, 2008, 54, (3), pp. 1617–1622.
    18. 18)
      • 1. Chia-Hsiang, Y., Tsung-Han, Y., Dejan, M.: ‘Power and area minimization of reconfigurable FFT processors: a 3GPP-LTE example’, IEEE J. Solid-State Circuits, 2012, 47, (3), pp. 757–768.
    19. 19)
      • 18. Shuenn, S.W., Chien, S.L.: ‘An area-efficient design of variable-length fast Fourier transform processor’, J. Signal Process. Syst., 2008, 51, pp. 245–256.
    20. 20)
      • 12. Kai-Jiun, Y., Shang-Ho, T., Chuang, C.H.: ‘MDC FFT/IFFT processor with variable length for MIMO-OFDM systems’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (4), pp. 720–731.
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