Online task scheduler in 3D-MCPs with TADVA

Online task scheduler in 3D-MCPs with TADVA

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and high-performance operating modes. The proposed DVA strategies can be employed in online, thermally constrained task schedulers. Three DVA strategies, random DVA, thermal-aware DVA (TADVA) and TADVA2.0, are proposed to reduce the temperature increase in 3D-MCPs by pre-emptively and dynamically estimating the optimum VAs for all cores in the processor during runtime once the chip begins operating. In particular, TADVA2.0 uses the temperature-variation rates of the cores and takes into account two important thermal behaviours of 3D-MCPs that can effectively limit the temperature increase in 3D-MCPs. Experimental results indicate that, when compared with two previous online thermally constrained task schedulers, the proposed task scheduler with their novel DVA strategy can reduce hotspot occurrences by ∼60% and improve throughput by ∼8%. These results indicate that the proposed TADVA2.0 strategy is an effective technique for suppressing hotspot occurrences and optimising throughput for 3D-MCPs subject to thermal constraints.


    1. 1)
      • 1. Zou, Q., Poremba, M., He, R., et al: ‘Heterogeneous architecture design with emerging 3D and non-volatile memory technologies’. Proc. 20th Asia and South Pacific Design Automation Conf., January 2015, pp. 785790.
    2. 2)
      • 2. Coudrain, P., Souare, P.M., Prieto, R., et al: ‘Experimental insights into thermal dissipation in TSV-based 3-D integrated circuits’, IEEE Design Test, 2016, 33, (3), pp. 2136.
    3. 3)
      • 3. Puttaswamy, K., Loh, G.H.: ‘Thermal analysis of a 3D die-stacked high-performance microprocessor’. Proc. ACM Great Lakes Symp. VLSI, GLSVLSI, 2006, pp. 1924.
    4. 4)
      • 4. Hung, W.L., Link, G., Xie, Y., et al: ‘Interconnect and thermal-aware floorplanning for 3D microprocessors’. Proc. Int. Symp. Quality Electronic Design (ISQED), March 2006, pp. 98104.
    5. 5)
      • 5. Hu, Y., Chen, S., Peng, L., et al: ‘Effective thermal control techniques for liquid-cooled 3D multi-core processors’. Proc. Int. Symp. Quality Electronic Design (ISQED), March 2013, pp. 815.
    6. 6)
      • 6. Chen, Y., Kursun, E., Motschman, D., et al: ‘Through silicon via aware design planning for thermally efficient 3-D integrated circuit’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2013, 32, (9), pp. 13351346.
    7. 7)
      • 7. Zhou, X., Yang, J., Xu, Y., et al: ‘Thermal-aware task scheduling for 3D multicore processors’, IEEE Trans. Parallel Distrib. Syst. (TPDS), 2010, 21, (1), pp. 6071.
    8. 8)
      • 8. Hanumaiah, V., Vrudhula, S., Chatha, K.S.: ‘Performance optimal online DVFS and task migration techniques for thermally constrained multi-core processors’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2011, 30, (11), pp. 16771690.
    9. 9)
      • 9. Yeo, I., Kim, E.J.: ‘Temperature-aware scheduler based on thermal behavior grouping in multicore systems’. Proc. Conf. Design, Automation and Test in Europe (DATE), April 2009, pp. 946951.
    10. 10)
      • 10. Cui, J., Maskell, D.L.: ‘A fast high-level event-driven thermal estimator for dynamic thermal aware scheduling’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2012, 31, (6), pp. 904917.
    11. 11)
      • 11. Yu, C., Lung, C.-L., Ho, Y.-L., et al: ‘Thermal-aware on-line scheduler for 3-D many-core processor throughput optimization’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), 2014, 33, (5), pp. 763773.
    12. 12)
      • 12. Cheng, Y., Zhang, L., Han, Y., et al: ‘Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (2), pp. 239249.
    13. 13)
      • 13. Cui, Y., Zhang, W., Chaturvedi, V., et al: ‘Decentralized thermal-aware task scheduling for large-scale many-core systems’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24, (6), pp. 20752088.
    14. 14)
      • 14. Murali, S., Mutapcic, A., Atienza, D., et al: ‘Temperature control of high-performance multi-core platforms using convex optimization’. Proc. Conf. Design, Automation and Test in Europe (DATE), 2008, pp. 110115.
    15. 15)
      • 15. Coskun, A., Ayala, J., Atienza, D., et al: ‘Dynamic thermal management in 3D multicore architectures’. Proc. Conf. Design, Automation and Test in Europe (DATE), 2009, pp. 14101415.
    16. 16)
      • 16. ‘Intel 64 and IA-32 architecture software developer's manual’. Available at, accessed date 2014 April.
    17. 17)
      • 17. Huang, W., Ghosh, S., Velusamy, S., et al: ‘Hotspot: a compact thermal modeling methodology for early-stage VLSI design’, IEEE Trans. Very Large Scale Integr. Syst. (TVLSI), 2006, 14, (5), pp. 501513.
    18. 18)
      • 18. ‘HotSpot5.0 temperature modeling tool’. Available at, accessed date 2013 August.
    19. 19)
      • 19. Huang, W., Sankaranarayanan, K., Skadron, K., et al: ‘Accurate, pre-RTL temperature-aware design using a parameterized, geometric thermal model’, IEEE Trans. Comput., 2008, 57, (9), pp. 12771288.
    20. 20)
      • 20. Krum, A.: ‘Thermal management’, in Kreith, F. (Ed.): ‘The CRC handbook of thermal engineering’ (Springer-Verlag, Berlin, Heidelberg, 2000), ch. 2.
    21. 21)
      • 21. Liu, Y., Yang, H., Dick, R.P., et al: ‘Thermal vs. energy optimization for DVFS-enabled processors in embedded systems’. Proc. Eighth Int. Symp. Quality Electronic Design (ISQED), March 2007, pp. 204209.
    22. 22)
      • 22. Yang, J., Zhou, X., Chrobak, M., et al: ‘Dynamic thermal management through task scheduling’. Proc. IEEE Int. Symp. Performance Analysis of Systems and software (ISPASS), April 2008, pp. 191201.
    23. 23)
      • 23. Li, J., Qiu, M., Niu, J.-W., et al: ‘Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads’, ACM Trans. Embed. Comput. Syst., 2013, 12, (2), pp. 24:124:22.
    24. 24)
      • 24. Liao, C.H., Lin, Y.Z., Wen, C.H.P.: ‘Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors’. Proc. Int. Symp. VLSI Design, Automation and Test (VLSI-DAT), April 2015, pp. 14.
    25. 25)
      • 25. ‘Alpha 21264/ev6 microprocessor hardware reference manual’. Available at hrm.pdf, accessed date 2013 August.
    26. 26)
      • 26. Skadron, K., Stan, M.R., Sankaranarayanan, K., et al: ‘Temperature-aware microarchitecture: modeling and implementation’, ACM Trans. Archit. Code Optim. (TACO), 2004, 1, (1), pp. 94125.
    27. 27)
      • 27. Liao, C.-H., Wen, C.H.-P., Chakrabarty, K.: ‘An online thermal-constrained task scheduler for 3D multi-core processors’. Proc. Conf. Design, Automation and Test in Europe (DATE), March 2015, pp. 351356.

Related content

This is a required field
Please enter a valid email address