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1887

access icon free Efficient ASIC and FPGA implementation of cube architecture

© The Institution of Engineering and Technology
Received 02/04/2016, Accepted 20/05/2016, Revised 03/05/2016, Published 23/08/2016

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix-2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field-programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high-speed application in microprocessor environment.

Inspec keywords: field programmable gate arrays; hypercube networks; application specific integrated circuits

Other keywords: Encounter(R) RTL Compiler RC13.10 v13.10-s006_1; addition operation; synthesis reports; generalised architecture; magnitude number; performance parameters; Vedic mathematics; cubic architecture; cadence tool; high-speed application; binary radix-2 number system; cube operation; decimal numbers; Yavadunam sutra; Xilinx ISE 14.1 software; microprocessor environment; FPGA implementation; ASIC implementation; digital platforms

Subjects: Logic and switching circuits; Multiprocessing systems

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