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access icon free High-performance elliptic curve cryptography processor over NIST prime fields

© The Institution of Engineering and Technology
Received 26/03/2016, Accepted 20/08/2016, Revised 15/07/2016, Published 23/08/2016

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224-bit and 256-bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area-efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area–delay product of this design is very low compared with similar designs. To the best of the authors’ knowledge, the ECP proposed in this study over performs better than available hardware in terms of area and timing.

Inspec keywords: public key cryptography; field programmable gate arrays; logic design; digital arithmetic; CMOS logic circuits; application specific integrated circuits

Other keywords: National Institute of Standards and Technology standard; ECP; word length 256 bit; word length 224 bit; hardware implementation; ECSM; high-performance elliptic curve cryptography processor; NIST prime fields; Jacobian coordinates; field-programmable gate array; combined point doubling-point addition architecture; FPGA; modular arithmetic; CMOS ASIC implementation; affine coordinates; application-specific integrated circuit; security applications; area-delay product; high-performance elliptic curve scalar multiplication; size 65 nm

Subjects: CMOS integrated circuits; Logic design methods; Logic and switching circuits; Digital arithmetic methods; Cryptography; Security aspects of hardware; Digital circuit design, modelling and testing; Logic circuits

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