%0 Electronic Article %A Yu-Cheng Liu %+ Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan %A Cheng-Yu Han %+ Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan %A Shih-Yao Lin %+ Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan %A James Chien-Mo Li %+ Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan %K PATH %K circuit simulation tools %K PSN %K leon3mp benchmark circuit %K least-square boosting %K timing-aware feature %K LSBoost %K SVR %K flip-flop transition in window %K support vector regression %K power supply noise %K feature extractions %K switching activity in window %K very large scale integration chip testing %K yield loss %K SAW %K PSN-aware circuit test timing prediction %K FFTW %K IOT method %K machine learning %K neural network %K physical-aware features %K raw data dimension reduction %K IR drop %K terminal FF transition of long paths %K circuit timing simulation %K input-output transition %X Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools. %@ 1751-8601 %T PSN-aware circuit test timing prediction using machine learning %B IET Computers & Digital Techniques %D March 2017 %V 11 %N 2 %P 60-67 %I Institution of Engineering and Technology %U https://digital-library.theiet.org/;jsessionid=1gsmkk5cfudci.x-iet-live-01content/journals/10.1049/iet-cdt.2016.0032 %G EN