Performance/energy aware task migration algorithm for many-core chips

Performance/energy aware task migration algorithm for many-core chips

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This study proposes an efficient task migration algorithm for mesh-based multi- and many-core chips. The proposed algorithm collects tasks running on a rectangular-based set of cores, that is, source sub-mesh and moves the tasks to another rectangular-based set to remove chip temperature hotspots and to provide balanced load on the chip. The proposed migration algorithm uses the concept of gathering/scattering to minimise the traffic induced by the migration. In this regard, the proposed algorithm uses a selected node in each row of the source sub-mesh to gather tasks of all cores in the same row. Selection of the gathering node is done based on its location in the row and traffic rate of other cores in the row. When gathering nodes are migrated, in the destination sub-mesh, then, they scatter their tasks according to the same pattern among the cores in their rows. Simulations of the proposed migration algorithm are done by Access Noxim simulator in a various range of network conditions with application graphs of D263DECMP3DEC, DMPEG4, and DVOPD. Results obtained from simulations show that the proposed algorithm offers 36% better performance, 28% lower energy consumption, and 7% lower temperature in comparison with the previously proposed migration algorithms.


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