access icon free Switchable cache: utilising dark silicon for application specific cache optimisations

Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. Only one cache configuration is active at any given time based on the application under execution, while all other configurations remain inactive (dark). They describe an architecture to enable seamless integration of multiple cache configurations, and a novel design space exploration methodology to rapidly pre-determine the optimal set of configurations at design-time, for a given group of applications. For design spaces containing trillions of design points, the authors’ exploration methodology always found the optimal solution in less than 2 s. The switchable cache improved memory access time by up to 26.2% when compared to a fixed cache.

Inspec keywords: transistors; optimisation; cache storage; power aware computing

Other keywords: transistors; exploration methodology; dark silicon; energy consumption; memory access patterns; multiple cache configurations; cache configuration; memory access time; switchable cache; application specific cache optimisations

Subjects: Performance evaluation and testing; Optimisation techniques; Memory circuits; Optimisation techniques; Semiconductor devices; Semiconductor storage

References

    1. 1)
      • 2. Cong, J., Xiao, B.: ‘Optimization of interconnects between accelerators and shared memories in dark silicon’. Proc. of the IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD'13), 2013.
    2. 2)
      • 19. Keogh, E., Chu, S., Hart, D., et al: ‘An online algorithm for segmenting time series’. Proc. IEEE Int. Conf. on Data Mining (ICDM'01), 2001.
    3. 3)
      • 1. Taylor, M.B.: ‘Is Dark Silicon Useful? harnessing the four horsemen of the coming dark silicon apocalypse’. Proc. of the Design Automation Conf. – (DAC'12), 2012, pp. 11311136.
    4. 4)
      • 15. Gordon-Ross, A., Lau, J., Calder, B.: ‘Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy’. Proc. 18th ACM Great Lakes Symp. on VLSI (GLSVLSI ‘08), New York, USA, 2008, pp. 379382.
    5. 5)
      • 10. Liang, Y., Mitra, T.: ‘Static analysis for fast and accurate design space exploration of caches'. Proc. Sixth IEEE/ACM Int. Conf. on Hardware/Software Co-Design and System Synthesis (CODES+ISSS'08), New York, USA, 2008, p. 103.
    6. 6)
      • 20. Muralimanohar, N., Balasubramonian, R., Jouppi, N.: ‘Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0’. Proc. 40th Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO'07), December 2007, pp. 314.
    7. 7)
      • 21. Nios II/f Core: Fast for Performance-Critical Applications.
    8. 8)
      • 3. Cota, E.G., Mantovani, P., Petracca, M., et al: ‘Accelerator memory reuse in the dark silicon era’, Comput. Archit. Lett., 2014, 13, (1), pp. 20122015.
    9. 9)
    10. 10)
      • 8. Janapsatya, A., Ignjatovic, A.: ‘Finding optimal L1 cache configuration for embedded systems’. Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC'06), 2006, pp. 16.
    11. 11)
      • 16. Zhang, C., Vahid, F.: ‘Cache configuration exploration on prototyping platforms’. Proc. 14th IEEE Int. Workshop on Rapid Systems Prototyping, 2003, pp. 164170.
    12. 12)
      • 22. Altera Qsys System Integration Tool.
    13. 13)
    14. 14)
      • 11. Schneider, J., Peddersen, J., Parameswaran, S.: ‘MASHffifog: a hardware-based multiple cache simulator for rapid fifo cache analysis’. Proc. of the Design Automation Conf. – (DAC'14), 2014.
    15. 15)
      • 13. Bokhari, H., Haris, J., Shafique, M., et al: ‘darkNoC: designing energy-efficient network-on-chip with multi-Vt cells for dark silicon’. Proc. 51st Annual IEEE/EDAC/ACM Design Automation Conf. (DAC'14), 2014.
    16. 16)
      • 9. Khatwal, R.: ‘Application specific cache simulation analysis for application specific instruction set processor’, Int. J. Comput. Appl., 2014, 90, (13), pp. 3141.
    17. 17)
      • 5. Gordon-Ross, A., Zhang, C., Vahid, F., et al: ‘Chapter 6 tuning caches to applications for low-energy embedded systems’, in Macii, E. (Eds.): ‘Ultra low-power electronics and design’ (Springer, 2004) pp. 103122.
    18. 18)
      • 6. Hill, M.D., Swift, M.M.: ‘Reducing memory reference energy with opportunistic virtual caching arkaprava basu’. Proc. 39th Annual Int. Symp. on Computer Architecture (ISCA'12), 2012.
    19. 19)
      • 12. Nawinne, I., Schneider, J., Javaid, H., et al: ‘Hardware-based fast exploration of cache hierarchies in application specific MPSoCs’. Proc. of the Design Automation and Test in Europe Conf. (DATE'14), March 2014.
    20. 20)
      • 7. Shwe, S.M.M., Javaid, H., Parameswaran, S.: ‘RExCache: rapid exploration of unified last-level cache’. Proc. 18th Asia and South Pacific Design Automation Conf. (ASP-DAC'13), January 2013, pp. 582587.
    21. 21)
      • 18. Viana, P., Gordon-Ross, A., Keogh, E., et al: ‘Configurable cache subsetting for fast cache tuning *’. Proc. of the Design Automation Conf. – (DAC'06), 2006, pp. 695700.
    22. 22)
      • 4. Turakhia, Y., Raghunathan, B., Garg, S., et al: ‘HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors’. Proc. 50th Annual ACM/EDAC/IEEE Design Automation Conf. (DAC'13), 2013.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2015.0114
Loading

Related content

content/journals/10.1049/iet-cdt.2015.0114
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading