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Defect avoidance in programmable devices

Defect avoidance in programmable devices

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Programmable logic devices permit a new way to practice yield improvement: redundancy at configuration time. By doing so, the authors avoid the overheads of traditional redundancy: explicit spares, replacement logic and on-chip non-volatile memory. This presentation describes a method for avoiding defects that also does not require a unique place-and-route for each fielded chip. Formal analysis and experimental results show the feasibility of the method for standard, unmodified field-programmable gate arrays.

References

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      • 2. Wells, R.W., Ling, Z.-M., Patrie, R.D., Tong, V.L., Cho, J., Toutounchi, S.: ‘Application-specific testing methods for programmable logic devices’. United States Patent Number: 6,817,006, 9 November 2004.
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      • 3. Trimberger, S.M.: ‘Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof’. US Patent 7,251,804, 31 July 2007.
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      • 4. Trimberger, S.M.: ‘Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits’. US Patent 7,424,655, 9 September 2008.
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      • 5. Rubin, R., DeHon, A.: ‘Choose-your-own-adventure routing: lightweight load time defect avoidance’. FPGA, 2009.
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