Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
- Author(s): Martin A. Trefzer 1 ; James A. Walker 1 ; Simon J. Bale 1 ; Andy M. Tyrrell 1
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View affiliations
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Affiliations:
1:
Department of Electronics, University of York, York YO10 5DD, UK
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Affiliations:
1:
Department of Electronics, University of York, York YO10 5DD, UK
- Source:
Volume 9, Issue 4,
July 2015,
p.
190 – 196
DOI: 10.1049/iet-cdt.2014.0146 , Print ISSN 1751-8601, Online ISSN 1751-861X

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Inspec keywords: field programmable gate arrays; flip-flops; MOSFET
Other keywords: digital array architecture; statistically enhanced high performance metal gate MOSFET compact models; virtual prototype; D-type flip-flop timing characteristics; multireconfigurable architecture; field programmable gate array; gate level; technology process; post-fabrication transistor-level optimisation; design optimisation case study; gold standard simulations; size 25 nm; hardware VLSI prototype; intrinsic stochastic variability; operating point; simulation program; prefabrication verification; transistor level configuration options; integrated circuit emphasis; next-generation FPGA architecture; programmable analogue architecture
Subjects: Insulated gate field effect transistors; Logic and switching circuits; Logic circuits
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