Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor
- Author(s): Gurtac Yemiscioglu 1 and Peter Lee 1
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Affiliations:
1:
School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK
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Affiliations:
1:
School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK
- Source:
Volume 9, Issue 5,
September 2015,
p.
239 – 247
DOI: 10.1049/iet-cdt.2014.0102 , Print ISSN 1751-8601, Online ISSN 1751-861X
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This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm2. Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.
Inspec keywords: digital signal processing chips; CMOS integrated circuits; logic design; low-power electronics; VLSI; integrated circuit design; clocks
Other keywords: CMOS logic; very-large-scale integration implementation; processor architecture; complementary metal oxide semiconductor process; clock frequencies; Austria Micro Systems; clocked adiabatic logic logarithmic signal processor; low-power logarithmic signal processor
Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Digital signal processing chips; Digital signal processing chips; CMOS integrated circuits; Logic design methods; Integrated circuits; Digital circuit design, modelling and testing
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