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access icon free Application-oriented cache memory configuration for energy efficiency in multi-cores

This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time.

References

    1. 1)
      • 14. Stratix IV GX Development Kit, http://www.altera.com/products/devkits/altera/kit-siv-gx.html, accessed August 2014.
    2. 2)
      • 9. Balakrishnan, S., Rajwar, R., Upton, M., Lai, K.: ‘The impact of performance asymmetry in emerging multicore architectures’. Proc. Int. Symp. Computer Architecture (ISCA'05), Madison, USA, 2005, pp. 506517.
    3. 3)
      • 13. eCos, http://www.ecos.sourceware.org/, accessed August 2014.
    4. 4)
      • 10. Silva, B., Cuminato, L., Bonato, V.: ‘Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors’. Proc. of the 2012 Int. Conf. Reconfigurable Computing and FPGAs (ReConfig'12), Cancún, México, 2012, pp. 16.
    5. 5)
    6. 6)
      • 6. Saez, J., Fedorova, A., Prieto, M., Vegas, H.: ‘Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors’. Proc. ACM Int. Conf. Computing Frontiers, Bertinoro, Italy, 2010, pp. 3140.
    7. 7)
    8. 8)
    9. 9)
      • 4. Becchi, M., Crowley, P.: ‘Dynamic thread assignment on heterogeneous multiprocessor architectures’. Proc. ACM Int. Conf. Computing Frontiers, Ischia, Italy, 2006, pp. 2940.
    10. 10)
      • 2. Asaduzzaman, A.: ‘Cache optimization for real-time embedded systems’. Ph.D. thesis, Florida Atlantic University, 2009.
    11. 11)
      • 11. Kuncheva, L.I., Rodríguez, J.J.: ‘An experimental study on rotation forest ensembles’. Proc. of the Seventh Int. Conf. on Multiple Classifier Systems, MCS'07, Springer-Verlag, Prague, Czech Republic, 2007, pp. 459468.
    12. 12)
      • 16. Felsenstein, J.: ‘Inferring phylogenies’ (Sinauer Associates, Inc., 2004).
    13. 13)
      • 17. Newman, M.: ‘Networks: an introduction’ (Oxford University Press, 2010).
    14. 14)
      • 12. Sanches, A., Cardoso, J., Delbem, A.: ‘Identifying merge-beneficial software kernels for hardware implementation’. Proc. of the 2011 Int. Conf. Reconfigurable Computing and FPGAs (ReConfig'12), Cancún, México, 2011, pp. 7479.
    15. 15)
    16. 16)
      • 7. Saez, J.C., Prieto, M., Fedorova, A., Blagodurov, S.: ‘A comprehensive scheduler for asymmetric multicore systems’. Proc. European Conf. on Computer Systems, Paris, France, 2010, pp. 139152.
    17. 17)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2014.0091
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