Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity

Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity

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Nowadays, multiprocessor system-on-chips (MPSoCs) are employed in a heterogeneous fashion, being composed of application-specific integrated circuits (ASICs) and processors that implement different instruction set architectures (ISAs). Because of that, there are two main issues. First, the lack of adaptability, since ASICs are designed for a specific purpose and cannot be changed after deployment; second, the necessity to code for different ISAs, which involves different tool chains which increases design time. In this scenario, the authors propose custom-reconfigurable arrays for multiprocessor systems (CReAMS), which is composed of multiple processors that implement a unique ISA, each of them coupled to an adaptive reconfigurable system, so it is possible to simultaneously exploit instruction-level and thread-level parallelism. Differently from most reconfigurable architectures there is no need to change the binary/source code, nor software development process or environment, which guarantees software compatibility; and in contrast to current MPSoCs used in embedded systems, it is capable of adapting to accelerate applications that were not considered at design time. Besides the obvious advantages in software productivity, CReAMS outperforms a multiprocessor with single-issue processors by 19% and reduces 70% of the energy consumption. In addition, CReAMS outperforms a four-issue out-of-order superscalar processor by 18% in a power budget scenario.


    1. 1)
      • 1. International Technology Roadmap for Semiconductors. Available at
    2. 2)
      • 2. Available at
    3. 3)
    4. 4)
      • 4. Beck, A.C.S., Carro, L.: ‘Dynamic reconfigurable architectures and transparent optimization techniques’ (Springer, 2010).
    5. 5)
      • 5. Theodoridis, G., Soudris, D., Vassiliadis, S.: ‘A survey of coarse-grain reconfigurable architectures and cad tools’. Fine- and Coarse-Grain Reconfigurable Computing. (Springer, 2007), pp. 89149.
    6. 6)
      • 6. Hauck, S., Fry, T., Hosler, M., Kao, J.: ‘The Chimaera reconfigurable functional unit’. Proc. IEEE Symp. FPGAs for Custom Computing Machines, Napa Valley, CA, 1997, pp. 8796.
    7. 7)
      • 7. Hauser, J.R., Wawrzynek, J.: ‘Garp: a MIPS processor with a reconfigurable coprocessor’. Proc. 1997 IEEE Symp. Field Programmable Custom Computing Machines, 1997, pp. 1221.
    8. 8)
      • 8. Sankaralingam, K., Nagarajan, R., Liu, H., et al: ‘Exploiting ILP, TLP and DLP with the polymorphous TRIPS architecture’. Proc. 30th Int. Symp. Computer Architecture, June 2003, pp. 422433.
    9. 9)
      • 9. Swanson, S., Michelson, K., Schwerin, A., Oskin, M.: ‘WaveScalar’. MICRO-36, Dec.2003.
    10. 10)
    11. 11)
      • 11. Vassiliadis, S., Gaydadjiev, G.N., Bertels, K.L.M., Panainte, E.M.: ‘The Molen programming paradigm’. Proc. Third Int. Workshop on Systems, Architectures, Modeling, and Simulation, Greece, July 2003, pp. 110.
    12. 12)
      • 12. Lysecky, R., Stitt, G., Vahid, F.: ‘Warp processors’. Proc. 41st Annual Design Automation Conf. (DAC '04). ACM, New York, NY, USA, 2004, pp. 659681.
    13. 13)
      • 13. Clark, N., Kudlur, M., Park, H., Mahlke, S., Flautner, K.: ‘Application-specific processing on a general-purpose core via transparent instruction set customization’. MICRO-37, December 2004, pp. 3040.
    14. 14)
      • 14. Watkins, M.A., Albonesi, D.H.: ‘Enabling parallelization via a reconfigurable chip multiprocessor’. Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, 2010. 37th Int. Symp. Computer Architecture, June 2010.
    15. 15)
      • 15. Lee, J., Wu, H., Ravichandran, M., Clark, N.: ‘Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications’. ISCA '10.2010, pp. 270279.
    16. 16)
      • 16. Koenig, R., Bauer, L., Stripf, T., et al: ‘KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture’. Design, Automation & Test in Europe Conf., 2010, pp. 819824.
    17. 17)
      • 17. Shi, K., Howard, D.: ‘Challenges in sleep transistor design and implementation in low-power designs’. Proc. Design Automation Conf., 2006, 43, pp. 113116.
    18. 18)
      • 18. Heinrich, J.MIPS R1000 User Manual. MIPS R1000 User Manual, 1997. Available at (

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