access icon free Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform

© The Institution of Engineering and Technology
Received 13/01/2014, Accepted 26/07/2014, Revised 21/05/2014, Published 06/11/2014

In this study, the authors present a multiplier-less, high-speed and low-power pipeline architecture with novel dual Z-scanning technique for lifting-based two-dimensional (2D) discrete wavelet transform (DWT). The proposed architecture is composed of pipeline one-dimensional row, column processors and five transposing registers. Moreover, it uses 4N temporal line buffers to process 2D DWT of image with N × N resolution. Multipliers are designed with shift-and-add logic to reduce the critical path to one adder. Dual Z-scanning method is employed to reduce the transposition buffers and latency. The proposed architecture is superior to the existed architectures in speed, power and hardware utilisation for similar throughput specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 10.1. The proposed architecture operates at a frequency of 353.107 MHz, when synthesised for Xilinx Virtex-IV series field programmable gate array. Frame processing rate of 340 frames/second for full high-definition video can be achieved at this frequency of operation. RTL of the proposed design is synthesised using UMC 180 nm technology complementary metal-oxide semiconductor (CMOS) standard cell library for application specific integrated circuit (ASIC) implementation. ASIC synthesis of 2D DWT core uses 20 358 logic gates and consumes only 20.83 mW power at 100 MHz frequency.

Inspec keywords: hardware description languages; discrete wavelet transforms; application specific integrated circuits; image resolution; pipeline processing

Other keywords: register transfer logic; application speciflc integrated circuit; Xilinx Virtex-IV series fleld programmable gate array; multiplier-less pipeline architecture; shift-and-add logic; VHDL; CMOS standard cell library; Xilinx ISE 10.1; ASIC synthesis; frequency 353.107 MHz; image resolution; dual Z-scanning technique; lifting-based two-dimensional discrete wavelet transform; full high-deflnition video

Subjects: Multiprocessing systems; Integral transforms; Logic design methods; Computer vision and image processing techniques; Integral transforms; Computer-aided circuit analysis and design; Optical, image and video signal processing; Parallel architecture

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