A fault-tolerant core mapping technique in networks-on-chip

Fatemeh Khalili; Hamid R. Zarandi

A fault-tolerant core mapping technique in networks-on-chip

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Author(s): Fatemeh Khalili ¹ and Hamid R. Zarandi ¹
- Affiliations: 1: Department of Computer Engineering and Information Technology, Amirkabir University of Technology, 242 Hafez Avenue, P.O. Box: 15875-4413, Tehran, Iran
Source: Volume 7, Issue 6, November 2013, p. 238 – 245
DOI: 10.1049/iet-cdt.2013.0032 , Print ISSN 1751-8601, Online ISSN 1751-861X

Received 14/02/2011, Accepted 15/08/2013, Revised 24/07/2013, Published

This study proposes a fault-tolerant technique on application mapping and spare core allocation in networks-on-chip. The proposed technique sets the place of spare cores among free non-faulty processing cores, dynamically. Here, dynamically setting means that the places of spare cores are tuned for each application and are not fixed in the platform statically. Some vertices of each application core graph can be known as critical, based on their vulnerabilities, the performance degradation and the energy consumption overheads because of negative impacts of failure recovery. This technique locates the spare cores near to the critical cores. As the main theoretical contribution, the problem of spare core placement and its impression on system fault-tolerance properties is discussed. Some metrics are investigated to be considered in spare core allocation. The results of 1 000 000 fault injection experiments show that the proposed technique leads to communication energy reductions and performance improvement, compared with related works.

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