Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays

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Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays

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© The Institution of Engineering and Technology
Published

It is well-known that any logical functionality can be implemented using the reconfigurability in field-programmable gate arrays (FPGAs). However, the reconfigurability is traded with the reduced functional performance, increased cost and increased configuration overheads. Hardwiring the interconnect fabric is gaining notice as an alternative solution to tackle the mentioned problems. In this article, first, the authors present that hardwired built-in crossbars that can improve the performance of the inter-processor communication. The authors conduct an analysis of functional performance, cost and configuration cost for soft and hard crossbar (SBAR and HBAR) interconnects. The queuing model is applied to compare soft and hard interconnects. A motion JPEG (MJPEG) case study suggests that HBAR achieve significantly better throughput and less cost compared to SBAR. Second, the authors present the effectiveness of the hardwired network-on-chip (NoC) in FPGAs. Considering the Æthereal NoC, an analysis is conducted to compare hard and soft NoCs. Consequently, the analysis, implementation and simulation indicate that the hardwired networks perform significantly better than soft networks.

Inspec keywords: video coding; network-on-chip; queueing theory; field programmable gate arrays

Other keywords: SBAR; HBAR; MJPEG case study; motion JPEG case study; queuing model; soft crossbar; hardwired network-on-chip; hard crossbar; Æthereal NoC; hardwired built-in crossbars; inter-processor communication; field-programmable gate arrays; reduced functional performance; FPGA; increased configuration overheads

Subjects: Queueing theory; Network-on-chip; Queueing theory; Logic circuits; Logic and switching circuits; Network-on-chip

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