© The Institution of Engineering and Technology
Low-power consumption and stability in static random access memories (SRAMs) is essential for embedded applications. This study presents a novel design flow for power minimisation of nano-complementary metal-oxide semiconductor SRAMs, while maintaining stability. A 32 nm high-κ/metal-gate SRAM has been used as an example circuit. The baseline circuit is subjected to power minimisation using a dual-threshold voltage assignment based on novel combined design of experiments and integer linear programming (DOE-ILP) approach. However, this leads to a 15% reduction in the static noise margin (SNM) of the cell. The conjugate gradient optimisation overcomes this SNM degradation, while reducing the power consumption. The final SRAM design shows 86% reduction in power consumption (including leakage) and 8% increase in the SNM compared with the baseline design. The variability analysis of the optimised cell is performed by considering the effect of 12 parameters. SRAM arrays of different sizes are constructed to demonstrate the feasibility of the proposed SRAM cell. To the best of the authors’ knowledge, this is the first study which makes use of DOE-ILP and conjugate gradient method for simultaneous stability and power optimisation in high-κ/metal-gate SRAM circuits.
References
-
-
1)
-
Thakral, G., Mohanty, S.P., Ghai, D., Pradhan, D.K.: `A DOE-ILP assisted conjugate-gradient approach for power and stability optimization in high-κ/metal-gate SRAM', Proc. 20th ACM/IEEE Great Lakes Symp. on VLSI, 2010, p. 323–328.
-
2)
-
M.R. Hestenes ,
E. Stiefel
.
Methods of conjugate gradients for solving linear systems.
J. Res. Natl. Bur. Stand.
,
6 ,
409 -
436
-
3)
-
S. Mukhopadhyay ,
K. Kim ,
H. Mahmoodi ,
K. Roy
.
Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled-CMOS.
IEEE J. Solid-State Circuits
,
6 ,
1370 -
1382
-
4)
-
E. Seevinck ,
F.J. List ,
J. Lohstroh
.
Static-noise margin analysis of MOS SRAM cells.
IEEE J. Solid-State Circuits
,
748 -
754
-
5)
-
S.O. Toh
.
Nanoscale SRAM Variability and Optimization.
-
6)
-
Alorda, B., Torrens, G., Bota, S.A., Segura, J.: `Static and dynamic stability improvement strategies for 6T CMOS low-power SRAM', Proc. Design, Automation, and Test in Europe, 2010, p. 429–434.
-
7)
-
E. Kougianos ,
S.P. Mohanty
.
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO.
Elsevier Microelectron. J.
,
1 ,
95 -
103
-
8)
-
S.R. Schmidt ,
R.G. Launsby
.
Understanding industrial design of experiments.
-
9)
-
Zhao, W., Cao, Y.: `New generation of predictive technology model for sub-45nm design exploration', Proc. Int. Symp. on Quality Electronic Design, 2006, p. 585–590.
-
10)
-
Lin, S., Kim, Y.B., Lombardi, F.: `A low leakage 9T SRAM cell for ultra-low power operation', Proc. ACM Great Lakes Symp. on VLSI, 2008, p. 123–126.
-
11)
-
Azam, T., Cheng, B., Cumming, D.: `Variability resilient low-power 7T-SRAM design for nano-scaled technologies', Proc. 11th IEEE Int. Symp. on Quality Electronic Design (ISQED), 2010, p. 9–14.
-
12)
-
T. Mizuno ,
J. Okamura ,
A. Toriumi
.
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs.
IEEE Trans. Electron Devices
,
11 ,
2216 -
2221
-
13)
-
S.P. Mohanty ,
J. Singh ,
E. Kougianos ,
D.K. Pradhan
.
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.
Elsevier VLSI Integr. J.
,
1 ,
33 -
45
-
14)
-
S.X.D. Tan ,
C.J.R. Shi ,
J.-C. Lee
.
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.
IEEE Trans. CAD of Integr. Circuits Syst.
,
12 ,
1678 -
1684
-
15)
-
Moradi, F., Wisland, D.T., Mahmoodi, H., Berg, Y., Cao, T.V.: `New SRAM design using body bias technique for ultra low power applications', Proc. Int. Symp. on Quality Design, 2010, p. 468–471.
-
16)
-
Moradi, F., Panagopoulos, G., Karakonstantis, G.: `Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology', Proc. IEEE 29th Int. Conf. on Computer Design (ICCD), 2011, p. 326–331.
-
17)
-
Liu, Z., Kursun, V.: `High read stability and low leakage cache memory cell', Proc. Int. Symp. on Circuits and Systems, 2007, p. 2774–2777.
-
18)
-
Okumura, S., Iguchi, Y., Yoshimoto, S.: `A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme', Proc. Int. Symp. on Quality Electronic Design, 2009, p. 659–663.
-
19)
-
Thakral, G., Mohanty, S.P., Ghai, D., Pradhan, D.K.: `A combined DOE-ILP based power and read stability optimization in nano-CMOS SRAM', Proc. 23rd IEEE Int. Conf. on VLSI Design, 2010, p. 45–50.
-
20)
-
Amelifard, B., Fallah, F., Pedram, M.: `Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-', Proc. Design Automation and Test in Europe, 2006, p. 1–6.
-
21)
-
Kulkani, J.P., Kim, K., Park, S.P., Roy, K.: `Process variation tolerant SRAM array for ultra low voltage applications', Proc. Design Automation Conf., 2008, p. 108–113.
-
22)
-
Singh, J., Mathew, J., Mohanty, S.P., Pradhan, D.K.: `A nano-CMOS process variation induced read failure tolerant SRAM cell', Proc. Int. Symp. on Circuits and Systems, 2008, p. 3334–3337.
-
23)
-
Ghai, D., Mohanty, S.P., Kougianos, E.: `Variability-aware optimization of nano-CMOS active pixel sensors using design and analysis of Monte Carlo experiments', Proc. Int. Symp. on Quality Electronic Design, 2009, p. 172–178.
-
24)
-
A. Agarwal ,
B. Paul ,
S. Mukhopadhyay ,
K. Roy
.
Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid-State Circuits
,
9 ,
1804 -
1814
-
25)
-
Agarwal, K., Nassif, S.: `Statistical analysis of SRAM cell stability', Proc. Design Automation Conf., 2006, p. 57–62.
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