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Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

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Partial reconfiguration suffers from low performance and thus its use is limited when the reconfiguration overhead is too high compared to the task execution time. To overcome this issue, the authors present a fast internal configuration access port (ICAP) controller, FaRM, providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as master accesses, ICAP overclocking, bitstream pre-load into a controller and bitstream compression technique, Offset-run length encoding (RLE), which is an improvement of the RLE algorithm. Combining these approaches allows us to achieve an ICAP theoretical throughput of 800 MB/S at 200 MHz. In order to complete our approach, we provide a cost model for the reconfiguration overhead for the system level that can be used during the early stages of development. The authors tested their approach on an Advanced Encryption Standard (AES) encryption/decryption architecture.


    1. 1)
      • Clemente, J.A., Gonzalez, C., Resano, J., Mozos, D.: `A hardware task-graph scheduler for reconfigurable multi-tasking systems', Int. Conf. Reconfigurable Computing and FPGAs, 2008, p. 79–84.
    2. 2)
    3. 3)
      • Xilinx Inc.: ‘Virtex-5 configuration user guide’ Xilinx, (2010).
    4. 4)
      • Bomel, P., Crenne, J., Ye, L., Diguet, J.-P., Gogniat, G.: `Ultra-fast downloading of partial bitstreams through Ethernet', Proc. 22nd Int. Conf. architecture of computing systems, ser. ARCS ‘09, 2009, Berlin, Heidelberg, Germany, p. 72–83, Springer-Verlag.
    5. 5)
      • Koch, D., Beckhoff, C., Teich, J.: `Bitstream decompression for high speed FPGA configuration from slow memories', Int. Conf. Field-Programmable Technology, 2007, ICFPT 2007, December 2007, p. 161–168.
    6. 6)
      • Santambrogio, M.D., Sciuto, D.: `Task scheduling with configuration prefetching and antifragmentation techniques on dynamically reconfigurable systems', Proc. Conf. Design, Automation and Test in Europe, ser. DATE '08, 2008, New York, NY, USA, ACM519–522. Available at, .
    7. 7)
      • Flynn, A., Gordon-Ross, A., George, A.D.: `Bitstream relocation with local clock domains for partially reconfigurable fpgas', Proc. Conf. on Design, Automation and Test in Europe, ser. DATE ‘09. 3001 Leuven, 2009, Belgium, p. 300–303., Available at: Design and Automation Association, .
    8. 8)
      • M. Liu , Z. Lu , W. Kuehn , A. Jantsch . Reducing FPGA reconfiguration time overhead using virtual configurations. ReCoSoC
    9. 9)
      • Xilinx Inc.: ‘LogiCORE IP XPS HWICAP datasheet’ Xilinx, (2010).
    10. 10)
      • R. Tessier , W. Burleson . Reconfigurable computing for digital signal processing: a survey. J. VLSI Signal Process. Syst Signal Image Video Technol. , 7 - 27
    11. 11)
      • K. Paulsson , M.H. Ubner , S. Bayar , J. Becker . Exploitation of run-time partial reconfiguration for dynamic power management in Xilinx Spartan III-based systems.
    12. 12)
      • Xilinx Inc: ‘Partial reconfiguration user guide’ Xilinx, 2010, p. 100.
    13. 13)
      • C. Kao . Benefits of partial reconfiguration. Xcell J. , 65 - 67
    14. 14)
      • K. Papadimitriou , A. Dollas , S. Hauck . Performance of partial reconfiguration in FPGA systems: a survey and a cost model. ACM Transactions on Reconfigurable Technology and Systems
    15. 15)
      • S. Guccione , D. Levi , P. Sundararajan . (1999) JBits: Java based interface for reconfigurable computing.
    16. 16)
      • ARDMAHN consortium: ‘ARDMAHN project’,
    17. 17)
      • Liu, M., Kuehn, W., Lu, Z., Jantsch, A.: `Run-time partial reconfiguration speed investigation and architectural design space exploration', Int. Conf. Field Programmable Logic and Applications, 2009, FPL 2009, August 2009.
    18. 18)
      • Ouni, B., Belaid, I., Muller, F., Benjemaa, M.: `Placement of hardware tasks on FPGA using the BEE algorithm', Int. Conf. Pervasive and Embedded Computing and Communication Systems (PECCS11), 2011.
    19. 19)
      • I. Belaid , F. Muller , M. Benjemaa . New three-level resource management enhancing quality of off-line hardware task placement on FPGA. Int. J. Reconfigurable Comput. (IJRC) , 65 - 67
    20. 20)
      • Siozios, K., Koutroumpezis, G., Tatas, K., Soudris, D., Thanailakis, A.: `DAGGER: a novel generic methodology for FPGA Bitstream generation and its software tool implementation', IEEE Int. Proc. 19th Parallel and Distributed Processing Symp., 2005, April 2005, p. 165.

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