Routing of asynchronous Clos networks

Routing of asynchronous Clos networks

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Clos networks provide theoretically optimal solution to build high-radix switches. Dynamically reconfiguring a three-stage Clos network is more difficult in asynchronous circuits than in synchronous circuits. This study proposes a novel asynchronous dispatching (AD) algorithm for general three-stage Clos networks. It is compared with the classic synchronous concurrent round-robin dispatching (CRRD) algorithm in unbuffered Clos networks. The AD algorithm avoids the contention in central modules using a state feedback scheme and outperforms the throughput of CRRD in behavioural simulations. Two asynchronous Clos networks using the AD algorithm are implemented and compared with a synchronous Clos network using the CRRD algorithm. The asynchronous Clos scheduler is smaller than its synchronous counterpart. Synchronous Clos networks achieve higher throughput than asynchronous Clos networks because asynchronous Clos networks cannot hide the arbitration latency and their data paths are slow. The asynchronous Clos scheduler consumes significantly lower power than the synchronous scheduler and the asynchronous Clos network using bundled-data data switches shows the best power efficiency in all implementations.


    1. 1)
      • C. Clos . A study of nonblocking switching networks. Bell Syst. Tech. J. , 5 , 406 - 424
    2. 2)
      • H.J. Chao , C.H. Lam , E. Oki . (2001) Broadband packet switching technologies: a practical guide to ATM switches and IP routers.
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • Rojas-Cessa, R., Lin, C.B.: `Scalable two-stage Clos-network switch and module-first matching', Proc. Workshop on High Performance Switching and Routing, 2006, p. 303–308.
    9. 9)
      • Oki, E., Kitsuwan, N., Rojas-Cessa, R.: `Analysis of space–space–space Clos-network packet switch', Proc. Int. Conf. Computer Communications and Networks, 2009, p. 1–6.
    10. 10)
      • Kim, J., Dally, W.J., Towles, B., Gupta, A.K.: `Microarchitecture of a high radix router', Proc. Int. Symp. on Computer Architecture, 2005, p. 420–431.
    11. 11)
      • Gómez, C., Gómez, M.E., López, P., Duato, J.: `Exploiting wiring resources on interconnection network: increasing path diversity', Proc. Euromicro Conf. Parallel, Distributed and Network-Based Processing, 2008, p. 20–29.
    12. 12)
    13. 13)
    14. 14)
      • J. Sparsø , S. Furber . (2001) Principles of asynchronous circuit design – a systems perspective.
    15. 15)
    16. 16)
    17. 17)
    18. 18)
    19. 19)
    20. 20)
    21. 21)
    22. 22)
      • D.J. Kinniment . (2007) Synchronization and arbitration in digital systems.
    23. 23)
    24. 24)
      • S.S. Patil . (1972) Forward acting .
    25. 25)
      • Golubcovs, S., Shang, D., Xia, F., Mokhov, A., Yakovlev, A.: `Modular approach to multi-resource arbiter design', Proc. IEEE Int. Symp. Asynchronous Circuits and Systems, 2009, p. 107–116.
    26. 26)
      • Golubcovs, S., Shang, D., Xia, F., Mokhov, A., Yakovlev, A.: `Multi-resource arbiter decomposition', Technical Report, 2009, Newcastle University, NCL-EECE-MSD-TR-2009-143.
    27. 27)
      • Shang, D., Xia, F., Golubcovs, S., Yakovlev, A.: `The magic rule of tiles: virtual delay insensitivity', Proc. Int. Workshop on Power and Timing Modelling, Optimization and Simulation, 2009, p. 286–296.
    28. 28)
      • Bystrov, A., Kinniment, D., Yakovlev, A.: `Priority arbiters', Proc. IEEE Int. Symp. Asynchronous Circuits and Systems, 2000, p. 128–137.
    29. 29)
      • Song, W., Edwards, D.: `An asynchronous routing algorithm for Clos networks', Proc. Int. Conf. Application of Concurrency to System Design, 2010, p. 67–76.
    30. 30)
      • Song, W., Edwards, D.: `A low latency wormhole router for asynchronous on-chip networks', Proc. Asia and South Pacific Design Automation Conf., 2010, p. 437–443.
    31. 31)
    32. 32)
    33. 33)
    34. 34)
      • Sutherland, I., Fairbanks, S.: `GasP: a minimal FIFO control', Proc. Int. Symp. Asynchronous Circuits and Systems, 2001, p. 46–53.

Related content

This is a required field
Please enter a valid email address