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Advanced calibration techniques for high-speed source–synchronous interfaces

Advanced calibration techniques for high-speed source–synchronous interfaces

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Advanced and dynamic calibration techniques for maximising the link performance of parallel source–synchronous interfaces are introduced and demonstrated in this study, using as a case study a 533 MHz DDR2 SDRAM memory interface implemented in 90 nm standard complementary metal-oxide-semiconductor (CMOS), whereas most of them have been validated at 800 MHz too. A novel dynamic strobe masking system (DSMS) has also been employed which, in contrast to traditional techniques, adjusts dynamically the length of the masking signal in real time, based on the incoming strobe. Furthermore, optimal data capture is achieved by employing a fast bit-deskew calibration engine, while also a novel I/O calibration scheme is included. Post-layout simulation results demonstrate that the dynamic calibration and skew compensation techniques employed improve the timing margin while providing advanced robustness over process, voltage and temperature variations.

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