http://iet.metastore.ingenta.com
1887

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

References

    1. 1)
    2. 2)
      • E. Vittoz . (2004) Low-power electronics design.
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
      • Amirtharajah, R., Wenck, J., Collier, J., Siebert, J., Zhou, B.: `Circuits for energy harvesting sensor signal processing', Forty-Third ACM/IEEE Design Automation Conf., 2006, p. 639–644.
    10. 10)
    11. 11)
      • Rodrigues, J.N., Akgun, O.C., Owall, V.: `A <1 pJ sub-vt cardiac event detector in 65 nm LL-HVT CMOS', Proc. 18th IEEE/IFIP Int. Conf. on VLSI and System-on-Chip (VLSI-SOC), 2010, p. 253–258.
    12. 12)
    13. 13)
    14. 14)
    15. 15)
      • J. Sparsø , S. Furber . (2001) Principles of asynchronous circuit design – a systems perspective.
    16. 16)
      • Lotze, N., Ortmanns, M., Manoli, Y.: `A study on self-timed asynchronous subthreshold logic', IEEE Int. Conf. on Computer Design (ICCD), October 2007, p. 533–540.
    17. 17)
      • Dean, M.E., Dill, D.L., Horowitz, M.: `Self-timed logic using current-sensing completion detection (CSCD)', Proc. IEEE Int. Conf. on Computer Design (ICCD): VLSI in Computers and Processors, October 1991, p. 187–191.
    18. 18)
      • Grass, E., Jones, S.: `Asynchronous circuits based on multiple localised current-sensing completion detection', Proc. Second Working Conf. on Asynchronous Design Methodologies, May 1995, p. 170–177.
    19. 19)
      • Lampinen, H., Vainio, O.: `Circuit design for current-sensing completion detection', Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May–June 1998, 2, p. 185–188.
    20. 20)
      • Varshavsky, V., Tsukisaka, M.: `Current sensor on the base of permanent pre-chargeable amplifier', IEEE Proc. Ninth Great Lakes Symp. on VLSI, 1999, p. 210–213.
    21. 21)
    22. 22)
    23. 23)
    24. 24)
      • Peeters, A.M.G.: `Single rail handshake circuits', 1996, PhD, Eindhoven University of Technology.
    25. 25)
      • Akgun, O.C., Rodrigues, J., Sparsø, J.: `Minimum-energy sub-threshold self-timed circuits: design methodology and a case study', Proc. 16th IEEE Int. Symp. on Asynchronous Circuits and Systems (ASYNC), 2010, p. 41–51.
    26. 26)
    27. 27)
      • Kol, R., Ginosar, R.: `A doubly-latched asynchronous pipeline', Proc. Int. Conf. on Computer Design (ICCD), 1997, p. 706–712.
    28. 28)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0118
Loading

Related content

content/journals/10.1049/iet-cdt.2010.0118
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address