© The Institution of Engineering and Technology
Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as disturbs, as well as other PCM specific faults. In this study, the authors identify these failures, analyse their behaviours and develop fault primitives/models that describe these faults accurately and effectively. In addition, the authors propose an efficient test algorithm, called March-PCM, to test for these faults and compare its performance to some previously developed test algorithms.
References
-
-
1)
-
A. Pirovano ,
A. Lacaita ,
A. Benvenuti ,
F. Pellizzer ,
S. Hudgens ,
R. Bez
.
Scaling analysis of phase-change memory technology.
IEEE Int. Electron Devices Meeting Technical Digest
,
29.6.1 -
29.6.4
-
2)
-
Lam, C.: `Phase-change memory', 65thAnnual Device Research Conf., June 2007, p. 223–226.
-
3)
-
U. Russo ,
D. Ielmini ,
A. Redaelli ,
A. Lacaita
.
Intrinsic data retention in nanoscaled phase change memories – Part I: Monte Carlo model for crystalization and percolation.
IEEE Trans. Electron Devices
,
12 ,
3032 -
3039
-
4)
-
Lacaita, A., Ielmini, D.: `Status and challenges of PCM modeling', 37thEuropean Solid State Device Research Conf., September 2007, p. 214–221.
-
5)
-
Itri, A., Ielmini, D., Lacaita, A., Pellizzer, F., Pirovano, A., Bez, R.: `Analysis and phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories', 42ndInt. Reliability Physics Symp., April 2004, p. 209–215.
-
6)
-
M.L. Bushnell ,
V.D. Agrawal
.
(2004)
Essentials of electronic testing for digital, memory and mixed-signal VLSI circuit.
-
7)
-
J.D. Maimon ,
K.K. Hunt ,
L. Burcin ,
J. Rodgers
.
Chalcogenide memory array: characterization and radiation effects.
IEEE Trans. Nucl. Sci.
,
6 ,
1878 -
1884
-
8)
-
A. Pirovano ,
A. Redaelli ,
F. Pellizzer
.
Reliability study of phase-change non-volatile memories.
IEEE Trans. Device Mater. Reliab.
,
3 ,
422 -
427
-
9)
-
Osada, K., Kawahara, T., Takemura, R.: `Phase change RAM operated with 1.5-V CMOS as low cost embedded memory', IEEE 2005 Custom Integrated Circuits Conf., September 2005, p. 431–434.
-
10)
-
J. Maimon ,
E. Spall ,
R. Quinn ,
S. Schnur
.
Chalcogenide-based non-volatile memory technology.
IEEE Proc. Aerospace Conf.
,
2289 -
2294
-
11)
-
Ramaswamy, S., Hunt, K., Maimon, D.: `Progress on design and demonstration of the 4Mb chalcogenide-based random access memory', Non-Volatile Memory Technology Symp., November 2004, p. 137–142.
-
12)
-
Wei, X., Shi, L., Rajan, W.: `Universal HSPICE model for chalcogenide based phase change memory elements', Non-Volatile Memory Technology Symp., November 2004, p. 88–91.
-
13)
-
A. Pirovano ,
A. Lacaita ,
F. Pellizzer ,
S. Kostylev ,
A. Benvenuti ,
R. Bez
.
Low-field amprphous state resistance and threshold voltage drift in chalcogenide materials.
IEEE Trans. Electron Devices
,
5 ,
714 -
719
-
14)
-
Lacaita, A.L., Redaelli, A., Ielmini, D.: `Programming and disturb characteristics in non volatile phase change memories', IEEE Non-Volatile Semiconductor Memory Workshop, August 2004, p. 26–27.
-
15)
-
Lai, S.: `Current status of the phase change memory and its future', IEEE Int. Electron Devices Meeting Technical Digest, December 2003, p. 10.1.1–10.1.4.
-
16)
-
Mantegazza, D., Ielmini, D., Pirovano, A.: `Electrical characterization of anomalous cells in phase change memory arrays', Int. Electron Devices Meeting, December 2006, p. 1–4.
-
17)
-
Bedeschi, F., Bez, R., Boffino, C.: `4-Mb MOSFET-selected phase-change memory experimental chip', 30thEuropean Solid-State Circuits Conf., September 2004, p. 207–210.
-
18)
-
Salamon, D., Cockbum, B.F.: `An electrical simulation model for the chalcogenide phase-change memory cell', Int. Workshop on Memory Technology, Design and Testing, July 2003, p. 86–91.
-
19)
-
Muller, G., Nagel, N., Pinnow, C.-U., Rohr, T.: `Emerging non-volatile memory technologies', 29thEuropean Solid-State Circuits Conf., September 2003, p. 37–44.
-
20)
-
K.-L. Cheng ,
J.-C. Yeh ,
C.-W. Wang ,
C.-T. Huang ,
C.-W. Wu
.
RAMSES-FT: a fault simulator for flash memory testing and diagnostics.
VLSI Test Symp.
,
281 -
286
-
21)
-
Ha, Y., Yi, J., Park, H.H.J.: `An edge contact type cell for phase change RAM featuring very low power consumption', Symp. on VLSI Technology Digest of Technical Papers, June 2003, p. 175–176.
-
22)
-
van de Goor, A., Al-Ars, Z.: `Functional memory faults: a formal notation and a taxonomy', Proc. 18th IEEE VLSI Test Symp., April 2000, p. 281–289.
-
23)
-
Mohammad, M.G., Terkawi, L., Albasman, M.: `Phase change memory faults', 19thInt. Conf. on VLSI Design, January 2006, p. 6–11.
-
24)
-
M.G. Mohammad ,
K.K. Saluja
.
Optimizing program disturb faults test using defect-based testing.
Trans. Comput. Aided Des. Integr. Circuits and Syst.
,
6 ,
905 -
915
-
25)
-
D. Mantegazza ,
D. Ielmini ,
A. Pirovano ,
A. Lacaita
.
Anomalous cells with low reset resistance in phase-change memory arrays.
IEEE Electron Device Lett.
,
10 ,
865 -
867
-
26)
-
Ottogalli, F., Pirovano, A., Pellizzer, F.: `Phase-change memory technology for embedded applications', 34thEuropean Solid-state Circuits Conf., September 2004, p. 293–296.
-
27)
-
Shi, L., Chong, T., Li, J.: `Thermal modeling and simulation of nonvolatile and non-rotating phase change memory cell', Non-Volatile Memory Technology Symp., October 2004, p. 83–87.
-
28)
-
Y. Hwang ,
J. Hong ,
S. Lee
.
Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology.
Int. Symp. on VLSI Technology, System and Applications
,
29 -
31
-
29)
-
Gill, M., Lowrey, T., Park, J.: `Ovonic unified memory – a high-performance nonvolatile memory technology for stand-alone memory and embedded applications', IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, February 2002, 1, p. 202–459.
-
30)
-
D. Ielmini ,
A. Lacaita ,
D. Mantegazza
.
Recovery and drift dynamics of resistance and threshold voltages in phase-change memories.
IEEE Trans. Electron Devices
,
2 ,
308 -
315
-
31)
-
Bedeschi, F., Resta, C., Khouri, O.: `An 8Mb demonstrator for high-density 1.8V phase-change memories', Symp. on VLSI Circuit Digest of Technical Paper, June 2004, p. 442–445.
-
32)
-
M.G. Mohammad ,
L. Al-Terkawi
.
Techniques for disturb fault collapsing.
J. Electron. Test. Theory Appl.
,
4 ,
263 -
268
-
33)
-
U. Russo ,
D. Ielmini ,
A. Redaelli ,
A. Lacaita
.
Modeling of programming and read performance in phase-change memories-part II: program disturb and mixed-scaling approach.
IEEE Trans. Electron Devices
,
2 ,
515 -
522
-
34)
-
A. van de Goor
.
(1998)
Testing semiconductor memories: theory and practice.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0083
Related content
content/journals/10.1049/iet-cdt.2010.0083
pub_keyword,iet_inspecKeyword,pub_concept
6
6