http://iet.metastore.ingenta.com
1887

Fault model and test procedure for phase change memory

Fault model and test procedure for phase change memory

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as disturbs, as well as other PCM specific faults. In this study, the authors identify these failures, analyse their behaviours and develop fault primitives/models that describe these faults accurately and effectively. In addition, the authors propose an efficient test algorithm, called March-PCM, to test for these faults and compare its performance to some previously developed test algorithms.

References

    1. 1)
      • J. Maimon , E. Spall , R. Quinn , S. Schnur . Chalcogenide-based non-volatile memory technology. IEEE Proc. Aerospace Conf. , 2289 - 2294
    2. 2)
      • Lam, C.: `Phase-change memory', 65thAnnual Device Research Conf., June 2007, p. 223–226.
    3. 3)
      • Muller, G., Nagel, N., Pinnow, C.-U., Rohr, T.: `Emerging non-volatile memory technologies', 29thEuropean Solid-State Circuits Conf., September 2003, p. 37–44.
    4. 4)
      • Ottogalli, F., Pirovano, A., Pellizzer, F.: `Phase-change memory technology for embedded applications', 34thEuropean Solid-state Circuits Conf., September 2004, p. 293–296.
    5. 5)
      • Bedeschi, F., Resta, C., Khouri, O.: `An 8Mb demonstrator for high-density 1.8V phase-change memories', Symp. on VLSI Circuit Digest of Technical Paper, June 2004, p. 442–445.
    6. 6)
      • A. Pirovano , A. Lacaita , A. Benvenuti , F. Pellizzer , S. Hudgens , R. Bez . Scaling analysis of phase-change memory technology. IEEE Int. Electron Devices Meeting Technical Digest , 29.6.1 - 29.6.4
    7. 7)
      • Gill, M., Lowrey, T., Park, J.: `Ovonic unified memory – a high-performance nonvolatile memory technology for stand-alone memory and embedded applications', IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, February 2002, 1, p. 202–459.
    8. 8)
      • Bedeschi, F., Bez, R., Boffino, C.: `4-Mb MOSFET-selected phase-change memory experimental chip', 30thEuropean Solid-State Circuits Conf., September 2004, p. 207–210.
    9. 9)
      • Salamon, D., Cockbum, B.F.: `An electrical simulation model for the chalcogenide phase-change memory cell', Int. Workshop on Memory Technology, Design and Testing, July 2003, p. 86–91.
    10. 10)
      • Wei, X., Shi, L., Rajan, W.: `Universal HSPICE model for chalcogenide based phase change memory elements', Non-Volatile Memory Technology Symp., November 2004, p. 88–91.
    11. 11)
      • Y. Hwang , J. Hong , S. Lee . Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology. Int. Symp. on VLSI Technology, System and Applications , 29 - 31
    12. 12)
      • Ramaswamy, S., Hunt, K., Maimon, D.: `Progress on design and demonstration of the 4Mb chalcogenide-based random access memory', Non-Volatile Memory Technology Symp., November 2004, p. 137–142.
    13. 13)
      • Osada, K., Kawahara, T., Takemura, R.: `Phase change RAM operated with 1.5-V CMOS as low cost embedded memory', IEEE 2005 Custom Integrated Circuits Conf., September 2005, p. 431–434.
    14. 14)
      • Ha, Y., Yi, J., Park, H.H.J.: `An edge contact type cell for phase change RAM featuring very low power consumption', Symp. on VLSI Technology Digest of Technical Papers, June 2003, p. 175–176.
    15. 15)
    16. 16)
      • Lacaita, A.L., Redaelli, A., Ielmini, D.: `Programming and disturb characteristics in non volatile phase change memories', IEEE Non-Volatile Semiconductor Memory Workshop, August 2004, p. 26–27.
    17. 17)
      • Lai, S.: `Current status of the phase change memory and its future', IEEE Int. Electron Devices Meeting Technical Digest, December 2003, p. 10.1.1–10.1.4.
    18. 18)
    19. 19)
    20. 20)
    21. 21)
    22. 22)
      • Mohammad, M.G., Terkawi, L., Albasman, M.: `Phase change memory faults', 19thInt. Conf. on VLSI Design, January 2006, p. 6–11.
    23. 23)
      • M.L. Bushnell , V.D. Agrawal . (2004) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuit.
    24. 24)
      • Shi, L., Chong, T., Li, J.: `Thermal modeling and simulation of nonvolatile and non-rotating phase change memory cell', Non-Volatile Memory Technology Symp., October 2004, p. 83–87.
    25. 25)
    26. 26)
    27. 27)
    28. 28)
      • Lacaita, A., Ielmini, D.: `Status and challenges of PCM modeling', 37thEuropean Solid State Device Research Conf., September 2007, p. 214–221.
    29. 29)
    30. 30)
      • van de Goor, A., Al-Ars, Z.: `Functional memory faults: a formal notation and a taxonomy', Proc. 18th IEEE VLSI Test Symp., April 2000, p. 281–289.
    31. 31)
      • A. van de Goor . (1998) Testing semiconductor memories: theory and practice.
    32. 32)
      • Mantegazza, D., Ielmini, D., Pirovano, A.: `Electrical characterization of anomalous cells in phase change memory arrays', Int. Electron Devices Meeting, December 2006, p. 1–4.
    33. 33)
      • Itri, A., Ielmini, D., Lacaita, A., Pellizzer, F., Pirovano, A., Bez, R.: `Analysis and phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories', 42ndInt. Reliability Physics Symp., April 2004, p. 209–215.
    34. 34)
      • K.-L. Cheng , J.-C. Yeh , C.-W. Wang , C.-T. Huang , C.-W. Wu . RAMSES-FT: a fault simulator for flash memory testing and diagnostics. VLSI Test Symp. , 281 - 286
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0083
Loading

Related content

content/journals/10.1049/iet-cdt.2010.0083
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address