Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Design and security evaluation of balanced 1-of-n circuits

Design and security evaluation of balanced 1-of-n circuits

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

A new design flow for security is presented. Cryptographic circuit specifications are first refined and then mapped to a secure power-balanced library consisting of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Logic optimisation tools are then applied to generate secure synchronous circuits for layout generation. The circuits generated are more efficient than balanced circuits generated by alternative techniques. A new method is presented for evaluating the security of such circuits. A security metric is introduced, which is based on the common selection function that is widely used in differential power analysis (DPA) attacks and a correlation measure similar to the one used in correlation power analysis (CPA) attacks. The metric enables the construction of a library of robust cryptograhic components including S-boxes that are more resistant to attack.

Inspec keywords: logic circuits; circuit layout; cryptography; logic design; computer crime; circuit optimisation

Other keywords: cryptographic circuit specification; differential power analysis attack; correlation power analysis; balanced 1-of-n circuit; security evaluation; DPA attack; robust cryptograhic component; secure synchronous circuit; correlation measure; N-nary logic; common selection function; secure power-balanced library; security metric; logic optimisation tool; layout generation; S-boxes

Subjects: Data security; Cryptography; Logic design methods; Digital circuit design, modelling and testing; Logic circuits

References

    1. 1)
      • Tiri, K., Verbauwhede, I.: `Design method for constant power consumption of differential logic circuits', Proc. Design Automation and Test in Europe – DATE 2005, 2005, p. 628–633.
    2. 2)
      • Kamoun, N., Bossuet, L., Ghazel, A.: `Experimental implementation of DPA attacks on AES design with Flash-based FPGA technology', Int. Conf. Systems, Signals and Devices – SSD 2009, 2009, p. 1–4.
    3. 3)
      • Yee, G., Sechen, C.: `̀Dynamic logic synthesis', IEEE Proc. CICC 1997, 1997.
    4. 4)
      • Toms, W., Edwards, D., Bardsley, A.: `Synthesizing heterogeneously encoded systems', IEEE Proc. ASYNC 2006, 2006.
    5. 5)
    6. 6)
      • Aigner, M., Mangard, M., Menicocci, R., Olivieri, M., Scotti, G., Trifiletti, A.: `A novel CMOS logic style with data independent power consumption', Proc. Int. Symp. Circuits and Systems – ISCAS 2005, 2005, p. 1066–1069.
    7. 7)
      • Aigner, M., Mangard, M., Menichelli, F.: `Side channel analysis resistant design flow', Proc. ISCAS 2006, 2006, p. 2909–2912.
    8. 8)
      • Waddle, J., Wagner, D.: `Fault attacks on dual-rail encoded systems', Proc. ACSAC 2005, 2005, p. 483–494.
    9. 9)
      • Moore, S., Anderson, R., Cunningham, P., Mullins, R., Taylor, G.: `Improving smart card security using self-timed circuits', IEEE Proc. ASYNC 2002, 2002.
    10. 10)
    11. 11)
    12. 12)
      • Tiri, K., Verbauwhede, I.: `A VLSI design flow for secure side-channel attack resistant IC's', Proc. Design Automation and Test in Europe – DATE 2005, 2005, p. 58–63.
    13. 13)
      • Brier, E., Clavier, C., Olivier, F.: `Correlation power analysis with a leakage model', Proc. Cryptographic Hardware and Embedded Systems – CHES 2004, 2004, (LCNS, 3156), p. 16–29.
    14. 14)
      • Kim, K., Liu, C., Kang, S.: `Implication graph based domino logic synthesis', Proc. ICCAD 1999, November 1999, p. 111–114.
    15. 15)
      • http://www.intrinsity.com.
    16. 16)
      • A.J. Menezes , P.C. Van Oorschot , S.A. Vanstone . (1997) Handbook of applied cryptography.
    17. 17)
      • Kocher, P., Jaffe, J., Jun, B.: `Differential power analysis', Proc. Advances in Cryptography – CRYPTO 1999, 1999, p. 388–397.
    18. 18)
    19. 19)
      • Newcastle University, ‘Cryptographic processing and processors’, U.K. Patent Appl. No. 0719455.8, Oct. 4, 2007.
    20. 20)
      • R. Anderson , E. Biham , L. Knudsen . Serpent: a proposal for the advanced encryption standard.
    21. 21)
      • http://csrc.nist.gov/publications/fips/fips197-197.pdf.
    22. 22)
      • Chantarawong, S., Noo-intara, P., Choomchuay, S.: `An architecture for ', Proc. ICEP 2004, 2004, p. 157–162.
    23. 23)
      • Biham, E., Shamir, A.: `Differential fault analysis of secret key cryptosystems', Proc. Advances in Cryptography – CRYPTO 1997, 1997, p. 513–525.
    24. 24)
      • Murphy, J., Yakovlev, A.: `An alternating spacer AES cryptoprocessor', Proc. ESSIRC 2006, 2006, p. 126–129.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2010.0042
Loading

Related content

content/journals/10.1049/iet-cdt.2010.0042
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address