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Integration schemes and enabling technologies for three-dimensional integrated circuits

Integration schemes and enabling technologies for three-dimensional integrated circuits

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Various integration schemes and key enabling technologies for wafer-level three-dimensional integrated circuits (3D IC) are reviewed and discussed. Stacking orientations (face up or face down), methods of wafer bonding (metallic, dielectric or hybrid), formation of through-silicon via (TSV) (via first, via middle or via last) and singulation level (wafer-to-wafer or chip-to-wafer) are options for 3D IC integration schemes. Key enabling technologies, such as alignment, Cu–Cu bonding and TSV fabrication, are described as well. Improved performance, such as lower latency and higher bandwidth, lower power consumption, smaller form factor, lower cost and heterogeneous integration of disparate functionalities, are made possible in the next generation of electronics products with the realisation of 3D IC.

References

    1. 1)
    2. 2)
      • Kapur, P., McVittie, J.P., Saraswat, K.C.: `Realistic copper interconnect performance with technological constraints', Proc. IEEE Interconnect Technology Conf., 2003, p. 235.
    3. 3)
      • P.G. Emma . Is 3D chip technology the next growth engine for performance improvement?. IBM J. Res. Dev. , 6
    4. 4)
      • Lu, J.-Q., Kumar, A., Kwon, Y.: `3-D integration using wafer bonding', Advanced Metallization Conf. (AMC2000), 2000, p. 515–521, vol. 16.
    5. 5)
      • International Technology Roadmap for Semiconductors (ITRS): 2004 Edition and updates.
    6. 6)
      • E. Beyne . (2006) 3D system integration technologies, Symp. VLSI Technology.
    7. 7)
      • C.S. Tan , R. Reif . Multi-layer silicon layer stacking based on copper wafer bonding. Electrochem. Solid-State Lett. , 6 , G147 - G149
    8. 8)
      • Chen, K.N., Fan, A., Tan, C.S., Reif, R.: `Evolution of microstructure during copper wafer bonding', TMS Annual Meeting, March 2003, San Diego, CA.
    9. 9)
    10. 10)
    11. 11)
    12. 12)
      • L. Ristic . (1994) Sensor technology and devices.
    13. 13)
      • Guarini, K.W., Topol, A.W., Ieong, M.: `Electrical integrity of state-of-the-art 0.13 µm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication', Proc. IEDM, 2002, p. 943–945.
    14. 14)
      • Chatterjee, R., Fayolle, M., Leduc, P.: `Three dimensional chip stacking using a wafer-to-wafer integration', Proc. IITC Conf., 4–6 June 2007, p. 81–83.
    15. 15)
    16. 16)
    17. 17)
      • Noh, H., Moon, K., Cannon, A., Hesketh, P.J., Wong, C.P.: `Wafer bonding using microwave heating of parylene for MEMS packaging', Proc. IEEE Int. Conf. Electronic Components and Technology, 2004, 1, p. 924.
    18. 18)
      • Gutmann, R., Lu, J., Yu, J.: `Copper metallization needs for wafer-level, three dimensional integration', 207thECS Meeting, 15–20 May 2005, Quebec City, Canada.
    19. 19)
      • Niklaus, F., Lu, J.-Q., McMahon, J.J.: `Wafer-level 3D integration technology platforms for ICs and MEMs', Proc. 22nd Int. VLSI Multilevel Interconnect Conf. (VMIC), 2005, p. 486–493, IMIC.
    20. 20)
      • Bower, C.A., Malta, D., Temple, D.: `High density vertical interconnects for 3D integration of silicon integrated circuits', Proc. 56th Electronic Components and Technology Conf., 2006, San Diego, CA, p. 399–403.
    21. 21)
      • Haond, M.: `Lateral isolation in SOI CMOS technology', Proc. IEEE SOS/SOI Tech. Conf., 1990, p. 117–118.
    22. 22)
      • Chen, K.-N., Lee, S.W., Andry, P.S.: `Structure design and process control for Cu bonded interconnects in 3D integrated circuits', 2006 Int. Electron Devices Meeting (IEDM), 11–13 December 2006, San Francisco, CA, p. 367–370.
    23. 23)
    24. 24)
    25. 25)
      • Wang, P.-I., Karabacak, T., Yu, J.: `Low temperature copper-nanorod bonding for 3D integration', Proc. Materials Research Society Symp., 2007, 970, p. 225–230.
    26. 26)
    27. 27)
    28. 28)
      • Gueguen, P., Di Cioccio, L., Rivoire, M.: `Copper direct bonding for 3D integration', IEEE Int. Interconnect Technology Conf., 2008, p. 61–63.
    29. 29)
      • Osborn, T., He, A., Lightsey, H.: `All-copper chip-to-substrate interconnects', Proc. IEEE Electronic Components and Technology Conf., 2008, p. 67–74.
    30. 30)
      • Lim, D.F., Singh, S.G., Ang, X.F., Wei, J., Ng, C.M., Tan, C.S.: `Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation', IEEE Int. Conf. 3D System Integration, 2009, 5306545.
    31. 31)
      • Lim, D.F., Singh, S.G., Ang, X.F., Wei, J., Ng, C.M., Tan, C.S.: `Application of self assembly monolayer (SAM) in Cu-Cu bonding enhancement at low temperature for 3-D integration', Advanced Metallization Conf., 2009.
    32. 32)
    33. 33)
      • Liu, F., Yu, R.R., Young, A.M.: `A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding', 2008 Int. Electron Devices Meeting (IEDM), 15–17 December 2008, San Francisco, CA.
    34. 34)
      • C.S. Tan , R.J. Gutmann , R. Reif . (2008) Wafer level 3-D ICs process technology.
    35. 35)
      • P. Garrou , C. Bower , P. Ramm . (2008) Handbook of 3D integrations: technology and applications of 3D integrated circuits.
    36. 36)
      • Yu, R.R., Liu, F., Polastre, R.J.: `Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding', 2009 Symp. on VLSI Technology and Circuits, 15–18 June 2009, Kyoto, Japan.
    37. 37)
      • Reif, R., Fan, A., Chen, K.-N., Das, S.: `Fabrication technologies for three-dimensional integrated circuits', Int. Symp. Quality Electronic Design (ISQED), 2002, p. 33–37.
    38. 38)
    39. 39)
    40. 40)
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